Patents Examined by Gary V. Harkom
  • Patent number: 5228124
    Abstract: In a reader in which a tablet and a cursor device are connected electrically to the reader and an indicated position of the cursor device on the tablet is converted to a coordinate signal to be outputted, the improved reader in which two cursor devices are connected to the reader, and the first cursor device is retained by one hand, and the second cursor device is retained by the other hand, and the two cursor devices are manipulated by both hands of the operator so as to shift them on the tablet whereby the reader outputs the coordinate signal for the drawing of a graphic, and setting the command to a CPU on the basis of the indication of each cursor device.
    Type: Grant
    Filed: December 3, 1991
    Date of Patent: July 13, 1993
    Assignee: Mutoh Industries, Ltd.
    Inventors: Ichiki Kaga, Tatsuyoshi Ikuta, Hiroyuki Furuichi, Shuzo Matsumoto, Tetsuya Iwanaga
  • Patent number: 4864526
    Abstract: An interpolator or decimator filter structure operable between two sampling rates (F.sub.s and 2F.sub.2), and in which two branches (21 and 23) of the structure are divided into low and high frequency sections by sampling switches (27 and 29). The high frequency section of one branch (21) incorporates a composite filter comprises of a nesting filter (1') and a nested filter 1. Each of these filters 1, 1' includes a digital coefficient multiplier (5,5'). The coefficient (K.sub.2) of the coefficient multiplier (5), part of the nested filter (1), is preset to a value such that 3 dB attenuation occurs at a point offset in frequency from one-half the lower sampling rate (F.sub.s).
    Type: Grant
    Filed: August 8, 1986
    Date of Patent: September 5, 1989
    Assignee: Plessey Overseas Limited
    Inventor: Nigel P. Dyer
  • Patent number: 4445172
    Abstract: A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.
    Type: Grant
    Filed: December 31, 1980
    Date of Patent: April 24, 1984
    Assignee: Honeywell Information Systems Inc.
    Inventors: Arthur Peters, Philip E. Stanley