Abstract: An instruction buffer includes a shift register having M storage elements to store instructions before the instructions are issued to an instruction decoder. The instruction buffer also includes control logic to issue the instructions from the shifter register to the instruction decoder and shift instructions in the shift register to fill vacant storage elements. The control logic detects when N consecutive storage elements are vacant and loads a first set of N instructions into the vacant storage elements. One or more of the storage elements occupied by the first set of instructions are treated as vacant, depending upon the position of a predetermined instruction in the first set of instructions, so that instructions can be shifted into the vacant storage elements.

Abstract: Method and apparatus for predicting the outcome of branch instructions subject to execution in a multiple processor digital computer. Pipelining is a popular technique to accelerate the data processing rate of modern computers, and in particular the RISC architecture class of workstations. Accurate prediction of branch instructions is exceptionally important to the efficient use of pipelines, in that erroneous predictions require both the purge and reload of all affected processor pipelines. According to the present invention, branch prediction is based upon a correlation between a history of successive prior branches and a specified branch instruction. In a preferred practice, a branch prediction table is created. The fields in the table are derived and thereafter updated based upon the correlated combination of outcomes from prior branches and the branch address under consideration.