Abstract: A system to facilitate configuration of infrastructure resources is described. The system includes a plurality of on-premises infrastructure appliances, each appliance including a plurality of infrastructure devices and an on-premises infrastructure controller to control the plurality of infrastructure devices. The system further includes a cloud services resource configuration manager, communicatively coupled to each of the on-premises infrastructure controllers, to configure each of the on-premises infrastructure appliances via a respective on-premises infrastructure controller.

Abstract: A warning is generated when a computer simulation controller is determined to have insufficient charge to permit use through an upcoming simulation sequence. Thus, responsive to a computer simulation having a first context and a computer simulation controller having a first voltage, a human-perceptible indication of low voltage is presented, whereas if the computer simulation has a second context typically requiring less input than the first context, no indication is presented if the controller has the same first voltage.

Abstract: A computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, and one or more additional electronic components configured to receive electrical power from the battery. The computing device may further include a first current detector configured to detect a total battery discharge current. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit for the battery. In response to at least determining the difference, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

Abstract: An integrated circuit includes a plurality of sub blocks configured to process an instruction according to an operating condition, a plurality of active counters configured to count an active time, which is a time for each of the plurality of sub blocks to process an instruction, and a Dynamic Voltage and Frequency Scaling (DVFS) controller configured to calculate power consumption of the plurality of sub blocks during a sample period based on the active time and adjust an operating condition of the plurality of sub blocks based on the power consumption.

Abstract: Systems and methods related to efficient system on chip (SoC) power delivery with adaptive voltage headroom control are described. A method for adaptively controlling voltage headroom for a system includes, in response to either a detection of a headroom violation by a per core voltage regulator headroom monitor or a detection of a voltage droop by a per core droop detector, independently throttle operating frequency of a respective core clock signal. The method further includes, in response to meeting a predetermined criterion: (1) lowering the operating frequency of the respective core clock signal, (2) monitoring headroom violation events and droop events at the lowered operating frequency, and (3) if monitored headroom violation events or monitored droop events continue to meet the predetermined criterion, changing the voltage set point associated with the motherboard voltage regulator to a second voltage set point corresponding to a higher voltage.

Abstract: Methods and systems for controlling current consumption by an electrical load of a first circuit board are described. In an example, a device of a first circuit board can measure a current being drawn by the electrical load of the first circuit board from a second circuit board. The device can generate a control signal based on a current difference between the measured current and a target current. The control signal can represent a load control parameter. The device can apply the control signal to the electrical load of the first circuit board to adjust a current consumption by the electrical load.

Abstract: Embodiments disclosed include methods and systems that adaptively, in real-time, evaluate data center performance, assess data center efficiency, data center sustainability, data center availability, compute performance, storage performance and provide data center customers with an overall data center performance rating, presented as a Total Resource Utilization Efficiency or TRUE score. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods. Other embodiments of the methods or systems include addition of newly defined metrics as categories or sub-categories to be used to calculate data center TRUE score.

Abstract: An information handling system includes a failsafe circuit connected to a first power control interconnect conductor, to a second power control interconnect conductor, and to a processor status interconnect conductor. A processor may provide a first level indicating an operational status of the processor to the processor status interconnect conductor when the processor is operational, and provide a second level indicating a non-operational status of the processor to the processor status interconnect conductor when the processor is non-operational. The failsafe circuit may assure, upon provision of the second level to the processor status interconnect conductor, that the first power control interconnect conductor will be in a first failsafe state and the second power control interconnect conductor will be in a second failsafe state.

Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

Abstract: The present disclosure discloses a power management circuit, a chip and an upgrade method therefor, and a server. In the circuit, one terminal of a micro controller unit is connected to a control board and a processor of the chip, and the other terminal of the micro controller unit is connected to a power management integrated circuit unit, a voltage conversion unit, and a voltage regulator unit. The micro controller unit receives operation instructions sent by the control board and the processor, stores the operation instructions, reads a power-on/off operation instruction in the operation instructions that is sent by the control board, and sends the power-on/off operation instruction to the power management integrated circuit unit to enable the power management integrated circuit unit performs corresponding control on the voltage conversion unit and the voltage regulator unit to complete a power-on/off operation on the processor.

Abstract: Methods and systems for power management are disclosed. The disclosed methods and system for power management may reduce the likelihood of a data processing system failing to meet power budget or other types of goals regarding power consumption, use, and/or provisioning. To reduce the likelihood of the data processing system failing to meet power related goals, the data processing system may include two power managers. An integrated power manager may manage power consumption based on a current-based, fast changing representation of the quantity of power being supplied by the power supplies. In contrast, a system power manager may manage power consumption based on digital representations of the power supplied by the power supplies, which may refresh the digital representations less quickly than the rate at which the analog current based representation is refreshed.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: A scheme to improve performance of power-constrained computers, comprising a heterogeneous mix of compute elements, by dynamically reacting to changes in the switching capacitance that present workload induces in each heterogeneous compute element and learning the coefficients of a power-frequency model for each compute element for the present workload. At each time step, the scheme forecasts a maximum frequency that the compute element can run at without exceeding an input power limit for a given workload. The scheme rapidly re-learns coefficients of the power model and rapidly adapts the frequency as the workload's characteristics shift ensuring that compute elements run at the maximum frequency they can while not exceeding the input power limit.

Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.

Abstract: A processor may identify that an external power source has begun powering a computing device. The processor may identify computational data in a volatile memory of the computing device. The processor may determine that the external power source does not have sufficient energy capacity to provide the computing device enough power to process the computational data at a first I/O throttling rate. The processor may increase the first I/O throttling rate to a second I/O throttling rate. The second I/O throttling rate may allow the computational data to be processed by the computing device with the energy capacity of the external power source.

Abstract: The present invention provides a processing circuit, a method, and an electronic device for multiple power supply ports. The processing circuit includes N control modules and a bus. Each control module is correspondingly connected to a power supply port. The communication interface of each control module is connected to the bus. The bus is a one-wire bus and is connected to a power line ground through a resistor. The control modules transmit value signals to the bus. The varied range of a first physical quantity of a bus signal carried by the bus is related to first physical quantities or second physical quantities of all target signals transmitted to the bus. The control module detects the first quantity of the bus signal through the communication interface and adjusts the operating parameter of the connected power supply port according to the varied range of the detected first physical quantity.

Abstract: A power saving system of a battery charger is provided. A control terminal of a first transistor receives a wake-up signal. A counter is connected to a first terminal of the first transistor. The counter determines whether or not a working period of the wake-up signal from the first transistor is larger than a time threshold to output a counting signal. When the counting signal indicates that the working period of the wake-up signal is not larger than the time threshold, the counter and electronic components of an electronic device are turned off, thereby saving power of a battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from a power saving mode to a normal operation mode. In the normal operation mode, the battery can supply power to the electronic device.

Abstract: In an example, a computing device includes a non-volatile storage device to store a basic input/output system (BIOS) variable. Further, the computing device includes a BIOS. During a boot process of the computing devices, the BIOS may read the BIOS variable from the non-volatile storage device. Further, the BIOS may detect that an application is to be deployed in the computing device based on the BIOS variable. Furthermore, the BIOS may load an application package from the non-volatile storage device into a volatile storage device and build an advanced configuration and power interface (ACPI) data structure with the application package loaded in the volatile storage device. Further, the BIOS may deploy the application using the ACPI data structure.

Abstract: Methods, systems, and apparatus, including computer-readable media, for environment monitoring and management. In some implementations, information indicating a planned usage level for usage of cloud computing services is accessed by a group of multiple computing environments over a period of time. Usage of cloud computing services is monitored for the group of multiple computing environments. A usage measure indicating an amount of usage of cloud computing services by the group of multiple computing environments is generated over the period of time. A cloud computing usage notification is generated based on the planned usage level and the usage measure. The cloud computing usage notification is provided for presentation by an electronic device.

Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.