Abstract: Memory circuit including a first word line, a first bit line, a second bit line, a first inverter, a second inverter, a P-type pass gate transistor and a pre-charge circuit. The first inverter is coupled to a first storage node. The second inverter is coupled to the first storage node and the first inverter. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The P-type pass gate transistor is coupled to the first word line, the first inverter and the second inverter. The pre-charge circuit is coupled to the first bit line or the second bit line. The pre-charge circuit is configured to charge the first bit line or the second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level.

Abstract: According to an embodiment, a cell state calculation apparatus includes the following elements. The database stores a function indicating a relationship between a voltage and a charged capacity of an active material. The active material amount calculation unit calculates an amount of an active material of the secondary cell by referring to the database and by using the voltage detected by the voltage detector and the current detected by the current detector while the secondary cell is charged or discharged. The open circuit voltage calculation unit calculates a function indicating a relationship between an open circuit voltage and a charged capacity of the secondary cell by referring to the database and by using the calculated amount of the active material.

Abstract: A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.

Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: A random bit cell includes a latch, a voltage selector, a first non-volatile storage element, and a second non-volatile storage element. The latch has a first terminal coupled to a first local bit line, and a second terminal coupled to a second local bit line. The first non-volatile storage element has a first terminal coupled to the first local bit line, and a second terminal coupled to the voltage selector. The second non-volatile storage element has a first terminal coupled to the second local bit line, and a second terminal coupled to the voltage selector. During an initial operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element are floating. During an enroll operation, the first terminals of the first non-volatile storage element and the second non-volatile storage element receive a program voltage from the voltage selector.

Abstract: A random access memory (RAM) includes a bit-line, a source-line, a memory cell connected to the bit-line and the source-line, and a read/write circuit connected to the bit-line and the source-line and including a negative differential resistance (NDR) device.

Abstract: Systems, apparatuses, and methods related to performing operations within a memory device are described. Such operations may be performed using data latched in multiple sense amplifiers that are distributed among a plurality of sense amplifiers of the memory device. For example, those sense amplifiers, among the plurality of sense amplifiers, storing data associated with the operation(s) can be determined, and the data can be selectively sent from the determined sense amplifiers to an operation unit, in which the operations are performed. The operations may be made without affecting a subsequent read command that requests data from the plurality of sense amplifiers.

Abstract: There are provided a memory device and an operating method thereof. While memory cells connected to a selected word line are being programmed, the memory device applies bit line voltages set to be different from each other depending on separation distances of channel structures from an edge of the selected word line to bit lines connected to the channel structures.

Abstract: A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches the redundancy column address signal, compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

Abstract: A nonvolatile memory device includes a control logic circuit that receives a read command from outside the nonvolatile memory device, a memory cell array which includes a plurality of memory cells connected to a plurality of word lines, an address generator that generates a plurality of addresses based on read information from the outside of the nonvolatile memory device, an address decoder sequentially selects a plurality of pages in at least one word line, which correspond to the plurality of addresses, a page buffer circuit that is connected to the memory cell array through a plurality of bit lines, and prepares a plurality of sequential data from memory cells connected to the selected pages by the address decoder, and an input/output circuit that continuously outputs the plurality of sequential data from the page buffer circuit to the outside of the nonvolatile memory device through data lines.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

Abstract: In a method for operating a semiconductor device, the method may include: sorting program states of a memory cell that stores multi-bit data into a plurality of groups; applying different bias voltages to bit lines corresponding to a selected group among the plurality of groups; applying a program voltage to a selected word line corresponding to the selected group; verifying whether each of selected memory cells corresponding to the selected word line is programmed to a respective target program state; applying an inhibition voltage to bit lines coupled to programmed memory cells; and selecting a next group to be programmed until the plurality of groups are programmed.

Abstract: A memory device includes a memory cell array comprising a plurality of antifuse memory cells coupled to a plurality of word lines, a plurality of voltage lines and a plurality of bit lines, and a first decoder suitable for generating a word line driving signal associated with a target memory cell among the plurality of antifuse memory cells in response to a first address, and asserting the word line driving signal at least twice during a program operation.

Abstract: An example device for performing a write operation using a spintronic Hall effect includes a Spin Hall Effect (SHE) structure, a Magnetic Tunnel Junction (MTJ) element, and processing circuitry. The MTJ element includes a free structure, a pinned structure, and a tunnel barrier arranged between the free structure and the pinned structure. The free structure comprises a plurality of free layers. The free structure is arranged with the SHE structure such that current in the SHE structure induces spin transfer into the free structure. The processing circuitry is configured to receive an instruction to set the MTJ element to a target state of a plurality of states and in response to receiving the instruction, generate electrical current through the spin Hall effect structure to modify a resistance of the MTJ element to correspond to the target state.