Abstract: An imaging device includes a first substrate including a photoelectric conversion layer that includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type and in which a plurality of photoelectric conversion units are provided; a second substrate that is joined to the first substrate and in which a readout circuit substrate that outputs a signal based on information detected by the plurality of photoelectric conversion units is provided; and an element isolation portion defined by a first opening provided so as to penetrate the second substrate and at least one of the first semiconductor layer and the second semiconductor layer, and each of the plurality of photoelectric conversion units is separated from each other by the element isolation portion.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.

Abstract: Back end of line (BEOL) metallization structures and methods according to aspects of the invention generally include forming an interconnect structure including a recessed via structure in an interlayer dielectric. The recessed via structure is lined with a liner layer and filled with a first metal such as copper, tungsten, aluminum, alloys thereof or mixtures thereof. The recessed portion is filled with a second metal such as tantalum, titanium, tungsten, cobalt, ruthenium, iridium, platinum, nitrides thereof, or mixtures thereof, which in combination with the liner layer provides effective barrier properties for the bulk first metal.

Abstract: The present invention relates to a lighting device comprising a plurality of light emitting diodes, LEDs. The plurality of LEDs is disposed on a substrate for emitting visible light from at least one first light output surface in an outgoing light direction. The lighting device includes also at least one ultra violet light emitting diode, UV LED, for emitting UV light from a second light output surface in the outgoing light direction. A phosphor layer is disposed on at least the plurality of LEDs such that the LEDs are covered by the phosphor layer. The second light output surface for emitting UV light from the at least one UV LED is mounted at a higher level than the at least first light output surface relative to the substrate in the outgoing light direction. The present invention also relates to a method for manufacturing the lighting device.

Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.

Abstract: This disclosure discloses an array substrate, a method for making the same, and a display apparatus. The array substrate comprises a display area and a peripheral area around the display area. The method comprises: forming an active layer of a low temperature polysilicon TFT in the peripheral area of the array substrate; forming a gate of a oxide TFT disposed in the same layer as a source and a drain of the low temperature polysilicon TFT in the display area of the array substrate, and forming an active layer of the oxide TFT electrically insulated from the gate of the oxide TFT above the gate of the oxide TFT; forming a source and a drain of the oxide TFT on the active layer of the oxide TFT.

Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.

Abstract: A magnetoresistance device is disclosed, comprising a bottom electrode, a magnetic tunneling junction (MTJ) disposed on the bottom electrode, a top electrode disposed on the magnetic tunneling junction, a first spacer disposed on the magnetic tunneling junction and covering a sidewall of the top electrode, and a second spacer disposed on the first spacer and conformally covering along a sidewall of the first spacer, a sidewall of the magnetic tunneling junction and a sidewall of the bottom electrode.

Abstract: Provided are an adhesive film, and an organic electronic device (OED) encapsulation product using the same. Dimensional stability, lifespan, and durability may be enhanced even when a panel of an organic electronic device is large-sized and formed as a thin film by controlling dimensional tolerance and edge angular tolerance of the adhesive film, thereby ensuring long-term reliability, and process yields may be enhanced when the adhesive film is applied to an automation process.

Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.

Abstract: A stabilized fluoride phosphor for light emitting diode (LED) applications includes a particle comprising manganese-activated potassium fluorosilicate and an inorganic coating on each of the particles. The inorganic coating comprises a silicate. A method of making a stabilized fluoride phosphor comprises forming a reaction mixture that includes particles comprising a manganese-activated potassium fluorosilicate; a reactive silicate precursor; a catalyst; a solvent; and water in an amount no greater than about 10 vol. %. The reaction mixture is agitated to suspend the particles therein. As the reactive silicate precursor undergoes hydrolysis and condensation in the reaction mixture, an inorganic coating comprising a silicate is formed on the particles. Thus, a stabilized fluoride phosphor is formed.

Abstract: A resin-encapsulated semiconductor device includes a bump electrode formed on an element surface side of a semiconductor chip, a conductive layer electrically connected to the bump electrode, and a resin encapsulation body covering the semiconductor chip, the bump electrode, and the conductive layer. On a back surface of the semiconductor chip that is flush with a back surface of the resin encapsulation body, a metal layer and a laminated film are formed. The laminated film is formed on a front surface of the conductive layer, and an external terminal is arranged on an inner side of an outer edge of the semiconductor chip.

Abstract: A liquid crystal display device includes: a first display panel; and a second display panel opposing to the first display panel. Each of the first and second display panel includes a plurality of source lines, a plurality of gate lines, a plurality of thin film transistors, and a plurality of pixel electrodes electrically connected to corresponding one of the thin film transistors. In a second display panel, at least two thin film transistors are electrically connected to a same second source line and a same second gate line.

Abstract: A process of forming a field effect transistor (FET) and a FET are disclosed. The process includes steps of forming a nitride semiconductor layer on a substrate; selectively growing an n+-region made of oxide semiconductor material on the nitride semiconductor layer and subsequently depositing oxide film on the n+-region; rinsing the oxide film with an acidic solution; forming an opening in the oxide film to expose the oxide semiconductor layer therein; and depositing a metal within the opening such that the metal is in direct contact with the n+-region.

Abstract: An ultraviolet light-emitting device including a substrate, a first conductive type semiconductor layer disposed on the substrate, a mesa disposed on the first conductive type semiconductor layer and including a second conductive type semiconductor layer and an active layer disposed between the semiconductor layers, a first contact electrode contacting the exposed first conductive type semiconductor layer around the mesa, a second contact electrode contacting the second conductive type semiconductor layer on the mesa, a passivation layer covering the first contact electrode, the mesa, and the second contact electrode and having openings disposed above the first and second contact electrodes, and first and second bump electrodes electrically connected to the first and second contact electrodes through the openings of the passivation layer, in which the mesa has depressions in plan view, and the first and second bump electrodes cover the openings and a portion of the passivation layer.

Abstract: An array board 11b includes a display section AA, a source line 20 connected to the display section AA, a test circuit 40 connected to the source line 20 and configured to test the display section AA, a panel-side image input terminal that is disposed such that the test circuit 40 is between the terminal and the display section AA and to which a signal to be supplied to the source line 20 is input, a terminal connection line 51 connecting the source line 20 to the pane-side image input terminal 35A and the terminal connection line 51 including the terminal connection line 51 at least a part of which overlaps the test circuit 40 and a flattening film (insulation film) 28 at least disposed between an overlapping portion of the test circuit 40 and the terminal connection line 51.