Abstract: A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type.A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed.

Abstract: In a process for the stabilization of a PN junction an oxide layer (12) is produced on a semiconductor substrate (11), and above this layer a nitride layer (13) is also produced. The oxide layer (12) is wet-chemically etched following the formation and etching of the nitride layer (13). Following the wet chemical etching of the oxide layer (12), the overlapping nitride (13) is re-etched. Dopant implantation takes place in the wet-chemically-etched region. This then is followed by a diffusion. A process of this type achieves high electrical stability for an electronic component. Thereupon, the photoresist (14) or any other type of layer covering the nitride (13) is removed.

Abstract: A method of fabricating a solid state device having chemically bound arsenic and phosphorous includes carrying out liquid phase epitaxial growth in the presence of partial pressures of arsenic and phosphorus.

Abstract: The invention discloses a method including the following processes (a) through (c) for forming impurity regions in a semiconductor device (a) a process that forms at least one second conductive type impurity-doped region by doping second conductive type impurity selectively to a predetermined region of a first conductive type semiconductor layer constituting a semiconductor substrate, (b) a process that forms on the surface of the semiconductor substrate a diffusion mask having a first opening for exposing at least one of the second conductive type impurity regions and having a second opening for exposing a part adjacent to at least one of the second conductive type impurity regions, (c) a process that forms the second conductive type impurity region and a low concentration second conductive type impurity region being in contact with the former by out-diffusing through the first opening the second conductive type impurity of the second conductive type impurity region and re-doping the out-diffused impurity th

Abstract: Herein disclosed are a method of producing a semiconductor device. Especially in a device constructed to have a defective circuit replaced by a redundant circuit, after a fuse is cut by exposure to a laser beam, a portion to be fused is irradiated in a predetermined gas atmosphere with an optical ray to selectively form a CVD film thereby to form a protection film over the fuse so that the formation of the protection film is simplified after the fuse is cut, whereby any rise in the production cost is suppressed while improving the production yield and reliability.

Abstract: According to the present invention, a method of manufacturing a semiconductor apparatus is provided which comprises the steps of (a) depositing a boron layer on a silicon substrate, and (b) thermally diffusing boron from said boron layer into said silicon substrate. The present invention, which is characteristically based on the solid phase diffusion process, enables even a thin layer to be deposited. Further, unlike the ion implantation process, the present invention enables an impurity to be uniformly diffused even into an inclined plane. Unlike the case where boron-containing glass is used as a diffusion source, the invention enables a sufficient amount of boron to be diffused even at a temperature lower than 1000.degree. C.

Abstract: Surface features of a semiconductor structure above a predetermined level are exposed for selective treatment (e.g., etching) by forming a layer of a solvent-expanded polymer on the surface of the structure, and allowing the layer to dry and cure, thereby relaxing to the predetermined level, at which it protects the underlying structure during treatment. Subsequently, the protective layer is removed by rinsing in a solvent.

Abstract: A method of fabricating a semiconductor device capable of handling high voltages includes forming a relatively thick epitaxial layer the top surface of which defines a plurality of generally V-shaped grooves, a pair of the grooves having formed therebetween active device regions, such pair of grooves acting as isolation regions including impurity regions extending on both sides of the groove through the epitaxial layer to a lower layer. A pair of grooves formed inward of the first-mentioned grooves contact active regions of the device into which the V-shaped portions extend, again with each such V-shaped portion having impurity regions extending on both sides thereof. The impurity regions associated with the V-shaped grooves are formed simultaneously with other active regions of the device.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum ground rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguosuly arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing the chips density and performance versus hardware turn-around-time.

Abstract: In a process for fabricating a semiconductor integrated circuit, a polysilicon layer deposited on the working surface of a silicon substrate is selectively oxidized and the polysilicon oxide layer is partially removed to form an opening. A chemical vapor deposition layer is formed on the entire surface and anisotropic etching of said chemical vapor deposition layer is performed to leave the chemical vapor deposition layer on the sidewall of the opening.

Abstract: A semiconductor device made of a II-VI compound semiconductor and having a p type semiconductor crystal. The p type semiconductor crystal is one obtained by growing the II-VI compound semiconductor crystal by relying on a liquid phase crystal growth process using a solvent comprised of one of Group II and Group VI elements constituting the Group II-VI compound semiconductor and having a higher vapor pressure over the other of these elements in an atmosphere comprised of the other of the elements having a lower vapor pressure under controlled vapor pressure of the atmosphere, and by doping into the solvent a p type impurity element selected from Group Ia and Ib elements in an amount of a range from 1.times.10.sup.-3 to 5.times.10.sup.-1 mol %. Thus, p type semiconductor crystals for use in semiconductor devices can be obtained easily from II-VI compound semiconductors. The present invention is especially effective in ZnSe crystals.

Abstract: A process for producing a predetermined doping level in side walls and bases of trenches which have been etched into semiconductor substrates which involves treating the substrate with a gaseous atmosphere containing organic compounds of silicon, oxygen and boron in amounts sufficient to form a boron silicate glass, thermally decomposing the organic compounds to form the boron silicate glass as a layer deposit along the side walls and the bases and thereafter diffusing the layer deposit into the side walls and the base. This is followed by removing the layer deposit remaining after the predetermined amount of diffusion has taken place.

Abstract: A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.

Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows in the intermediate oxide layer between the two silicon layers and, before final etching of the two silicon layers and the intermediate oxide, application of a mask formed in such a manner as to superimpose on the second silicon layer in the transistor areas coverings wider than the corresponding windows of the intermediate oxide layer.

Abstract: A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorous and arsenic. Arsenic or antimony or the like, which are N type impurity material of which the energy of combination with vacancies is great are diffused in the P type base layer.

Abstract: A sensor element arrangement for a pyrodetector has a concave mirror with a sensor element arranged at a focus of the concave mirror and further sensor elements arranged laterally therefrom. Electrodes of both polarities are present on each side of the film, these electrodes being respectively separated from one another by quasi-meander-like, metal-free strips which engage into one another in the form of hook portions. The electrodes on the upper side reside opposite corresponding electrodes on the lower side for the formation of the sensor elements, and these electrodes are connected to one another at edge regions by connection lines. The sensor element arrangement together with the film and the connection lines is surrounded by a retaining frame which is insertable into the mounting of the concave mirror in centered and adjusted fashion.

Abstract: A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: In a power MOS FET and the method of manufacturing such FET, in which a material, such as platinum, having a small resistivity compensation effect is diffused as a lifetime killer into the vicinity of a PN diode junction formed by the drain region and the base region. The diffusion is made through an opening formed in a covering insulator layer. An example of the lifetime killer is platinum and the preferable temperature range for diffusing platinum is not higher than 900.degree.C.

Abstract: The present method provides for formation of isolation oxide without "bird-beak" extensions thereof through the use of a nitride mask in contact with the surface of a semiconductor substrate on both sides of a patterned oxide layer, on which substrate the isolation oxide is grown.

Abstract: A radiation hardened silicon-on-insulator semiconductor device and method of making the same is disclosed. A region is formed in the silicon layer adjacent the insulating substrate which has a high density of naturally occurring crystallographic defects. This region substantially reduces the back-channel leakage that occurs when the device is operated after being irradiated.