Patents Examined by Giovanni Astacio-Oquendo
  • Patent number: 11972708
    Abstract: An electronic panel includes a base substrate having a first area, a second area adjacent to the first area, and a third area adjacent to the second area, a plurality of pixels in the second area, a plurality of pixel signal lines in the third area and connected to the pixels, a crack detecting pattern spaced apart from the pixels and in the first area, a first line spaced apart from the pixel signal lines, in the third area, and connected to a portion of the crack detecting pattern, and a second line spaced apart from the pixel signal lines, in the third area, connected to another portion of the crack detecting pattern, and spaced apart from the first line. The crack detecting pattern has a line-symmetrical shape with respect to a symmetry axis passing through a center of the first area.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: April 30, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeongyun Han, Jong-Hwa Kim, Kyungsu Lee
  • Patent number: 11965848
    Abstract: A method for determining the electrical properties of a core sample having an initial saturation Sw0, an initial true resistivity Rt0, and a porosity ?, including the steps: preparing a brine having a resistivity Rw, flushing the core sample with the brine, determining a first true resistivity Rt1 at a first saturation Sw1, once the resistivity Rw of the brine going into the core sample is the same as the resistivity Rw of the brine going out of the core sample, determining a function Rt=f(Sw) describing the dependency of the true resistivity Rt of the core sample and the saturation Sw in the core sample, based on the initial saturation Sw0, initial true resistivity Rt0, first true resistivity Rt1, and first saturation Sw1, second true resistivity Rt2, and first saturation Sw2, determining the resistivity Ro of the fully saturated core sample by estimating the function Rt=f(Sw) to full saturation of the core sample at Sw=100%, determining a resistivity index I R = R t R o at the Sw, Sw1, Sw2 d
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: April 23, 2024
    Assignee: SAUDI ARABIAN OIL COMPANY
    Inventors: Atul Godbole, Sultan Muhammad Al Enezi
  • Patent number: 11965917
    Abstract: A power measurement device includes: a first three-phase to two-phase converter converting a three-phase voltage signal of three-phase AC power into a two-phase voltage signal; a second three-phase to two-phase converter converting a three-phase current signal of the three-phase AC power into a two-phase current signal; an instantaneous power calculator calculating an instantaneous value of active power of the three-phase AC power and an instantaneous value of reactive power of the three-phase AC power based on the two-phase voltage signal and the two-phase current signal; a first moving average calculator calculating multiple active power average values of different moving average data quantities; a second moving average calculator calculating multiple reactive power average values of different moving average data quantities; and calculators that calculate average active powers corresponding to a frequency of the three-phase AC power, and the reactive power corresponding to the frequency of the three-phase A
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: April 23, 2024
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Yasuaki Mitsugi, Takashi Shigemasa
  • Patent number: 11965858
    Abstract: An elastic matrix determination method for a laminated iron core, which can optimally determine a shear modulus in two planes including a laminating direction of the laminated iron core included in an elastic matrix in a constitutive equation representing a stress-strain relationship used for vibration analysis, and also provided is a vibration analysis method. When performing a vibration analysis of a laminated iron core formed by laminating steel sheets using a constitutive equation representing a stress-strain relationship in a matrix representation, a shear modulus in two planes including a laminating direction of the laminated iron core included in an elastic matrix in the constitutive equation is determined depending on an average tightening pressure in the laminating direction of the laminated iron core.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 23, 2024
    Assignee: JFE STEEL CORPORATION
    Inventor: Misao Namikawa
  • Patent number: 11959938
    Abstract: A package substrate, an apparatus for testing power supply noise, and a method for testing power supply noise are provided. The package substrate includes multiple pad arrays, and each of the multiple pad arrays at least includes power supply pads. Power supply pads belonging to a same power supply type in the multiple pad arrays are divided into a test pad and a power supply pad set. The power supply pad set includes power supply pads, other than the test pad, among the power supply pads belonging to the same power supply type, all the power supply pads in the power supply pad set are electrically connected together, and the test pad is configured to perform noise testing of at least one internal power supply corresponding to the same power supply type in a chip to be tested.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: April 16, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Honglong Shi, Maosong Ma, Jianbin Liu
  • Patent number: 11959948
    Abstract: Disclosed is a high voltage signal and low voltage signal sampling and transmission system based on a high voltage MCU, including a sampling unit, a high voltage processing unit, a communication unit and a low voltage processing unit. The sampling unit includes a bus voltage sampling module, a phase voltage detection module and an IGBT temperature detection module. The high voltage processing unit adopts the high voltage MCU, and the high voltage MCU is configured to perform state monitoring and analog-to-digital conversion on the three-way analog detection signals, and output a digital signal to the communication unit; the communication unit adopts an isolated communication unit to transmit the three-way digital signal converted by the high voltage MCU to the low voltage processing unit; the low voltage processing unit adopts a low voltage MCU to realize sampling and communication of high and low voltage sampling signals.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: April 16, 2024
    Assignee: JEE AUTOMATION EQUIPMENT (SHANGHAI) CO., LTD.
    Inventors: Lei Liu, Minsheng Jiao, Lin Zhang, Yanqi Guo
  • Patent number: 11959779
    Abstract: A pest monitoring system may include a sensor and a sensor unit. The sensor may be configured to measure a change in fringe capacitance. The sensor unit may include a housing, at least one microprocessor, a non-volatile memory, a transceiver, a clock, and a connector operatively connected to the sensor. The housing may include a power source. The sensor unit may be programmed to manage power usage.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: April 16, 2024
    Assignee: BRANDENBURG (UK) LIMITED
    Inventors: Mathew V. Kaye, Mark Jacques
  • Patent number: 11961823
    Abstract: Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 16, 2024
    Assignee: XILINX, INC.
    Inventors: Praful Jain, Martin Voogel, Brian Gaide
  • Patent number: 11946847
    Abstract: An extracellular potential measurement device includes multiple insulating films each of which is made from an electric insulating material, the insulating films being stacked and bonded to each other; and multiple electrode wires each of which is made from an electroconductive material, the electrode wires being arranged in multiple heights. Each of the electrode wires is interposed between an upper insulating film and a lower insulating film. Each of the insulating films, except for a lowermost insulating film, has an opening penetrating the insulating film. The opening in a lower insulating film has a size that is less than that of the opening in an upper insulating film, the openings in the insulating films being overlapped to form a recess having a size reducing downward, the recess being adapted to store a collection of cells. Each of the electrode wires has an end that is located near an opening in an insulating film that is immediately below the electrode wire, the ends being exposed in the recess.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 2, 2024
    Assignees: NOK CORPORATION, THE UNIVERSITY OF TOKYO
    Inventors: Takayuki Komori, Keiichi Miyajima, SooHyeon Kim, Teruo Fujii, Shinji Okawa
  • Patent number: 11942896
    Abstract: A device (9) for protecting a direct current electrical system (1) having one or more modules (2) from electric arcs comprises: a first sensor (10) provided with a first ring of ferromagnetic material configured to generate a first signal, representing a oscillating component of a current flowing through a cable inserted into the ring; a conditioning stage (12), having a bandpass filter, for conditioning the first signal; a first threshold comparator (13); a counter (15); a processor (14); a second sensor (19), configured to generate a second signal representing a direct current component of the current flowing through the cable; a second threshold comparator (20).
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 26, 2024
    Assignee: SOCIETA' ELETTRICA S.R.L.
    Inventors: Euro Marangoni, Armando Randi, Carlo Bambi
  • Patent number: 11936397
    Abstract: A composite analog-to-digital converter (ADC) has a low resolution ADC configured to receive and digitize analog data, the low resolution ADC having a low resolution and a high operating speed, one or more high resolution ADCs configured to receive and digitize the analog data, the one or more high resolution ADCs having a resolution higher than the low resolution ADC, and an operating speed lower than the high operating speed of the low resolution ADC, a sample clock generator to provide a sample clock signal to the low resolution ADC and to a clock divider, a mixer to receive the analog data and connected to the one or more high resolution ADCs, a local oscillator connected to the mixer to allow the one or more high resolution ADCs to be tuned to sample a portion of a spectrum of the first ADC. A test and measurement instrument contains a composite ADC.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: March 19, 2024
    Assignee: Tektronix, Inc.
    Inventor: Alexander Krauska
  • Patent number: 11933861
    Abstract: A method and apparatus for performing an on-system built-in self-test of a converter are provided. In the method, a controller generates a test signal and outputs the test signal to the converter. The controller receives a response signal from the converter and determines a plurality of bin powers of a plurality of bins, respectively, of a frequency domain signal representative of the response signal. The controller determines a figure of merit for the converter based on a first bin power of a first bin of the plurality of bin powers, where the first bin corresponds to a frequency of the test signal.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 19, 2024
    Assignee: STMicroelectronics International N.V.
    Inventors: Ankur Bal, Sharad Gupta
  • Patent number: 11933825
    Abstract: A system frequency detector includes an orthogonal coordinate signal generator generating an orthogonal two-phase voltage signal from a three-phase voltage signal of three-phase alternating current power by converting the three-phase voltage signal into a two-phase voltage signal orthogonal to the three-phase voltage signal, converting the two-phase voltage signal into a voltage signal of a rotating coordinate system, calculating a moving average of the voltage signal of the rotating coordinate system, and performing an inverse transformation of the voltage signal of the rotating coordinate system after calculating the moving average. A frequency calculator calculates an angular frequency based on the two-phase voltage signal, and an arithmetic unit calculates a system frequency of the power system from the angular frequency.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 19, 2024
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Yasuaki Mitsugi, Takashi Shigemasa
  • Patent number: 11933831
    Abstract: A method for monitoring at least one Y-capacitance of an electrical on-board power supply of a vehicle includes ascertaining a current capacitance value of the at least one Y-capacitance and a current on-board power supply voltage of the electrical on-board power supply. The method further includes determining a currently stored amount of energy in the at least one Y-capacitance depending on the current on-board power supply voltage of the electrical on-board power supply and the current capacitance value of the at least one Y-capacitance of the electrical on-board power supply, comparing the currently stored amount of energy in the at least one Y-capacitance to a predetermined threshold value, and generating a control signal when the predetermined threshold value is exceeded in the comparing.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 19, 2024
    Assignee: Mercedes-Benz Group AG
    Inventors: Urs Boehme, André Haspel
  • Patent number: 11927622
    Abstract: An abnormality resulting from connection between a plurality of substrates is easily detected in a semiconductor device including a multilayer semiconductor substrate. The semiconductor device includes a plurality of semiconductor substrates, a connection member, a power supply terminal, and an observation terminal. The connection member is electrically connected on joint surfaces of the plurality of semiconductor substrates to form at least one connection line that extends over the plurality of semiconductor substrates. The power supply terminal is connected to one end of the connection line, and the observation terminal is connected to the other end of the connection line. Power is supplied to the power supply terminal. The observation terminal is used to observe a resistance state of the connection line.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 12, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masashi Tokunaga
  • Patent number: 11921153
    Abstract: Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: March 5, 2024
    Assignee: SK hynix Inc.
    Inventor: Tae-Pyeong Kim
  • Patent number: 11923670
    Abstract: An arc detection device includes: a low-impedance circuit connected between a node on wiring connecting the positive electrode of a DC/DC converter and a plurality of DC/DC converters, extending from the positive electrode of the DC/DC converter, and branching toward the plurality of DC/DC converters and a node on wiring connecting the negative electrode of the DC/DC converter and the plurality of DC/DC converters, extending from the negative electrode of the DC/DC converter, and branching toward the plurality of DC/DC converters; an electric current detector that detects an electric current flowing through the low-impedance circuit; and an arc determiner that determines, on the basis of the electric current detected by the electric current detector whether an electric arc has occurred.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: March 5, 2024
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tatsuo Koga, Kazunori Kidera, Keita Kanamori
  • Patent number: 11923325
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • Patent number: 11921137
    Abstract: According to one embodiment, an anomaly detection apparatus includes a processing circuit configured to calculate a reconstruction error of an input signal being a time-series signal, calculate cycle information indicating cyclic property of the reconstruction error, and determine presence/absence of an anomaly signal in the input signal on the basis of the cycle information or the cycle information and the reconstruction error.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 5, 2024
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Tenta Sasaya, Takashi Watanabe, Toshiyuki Ono
  • Patent number: 11921148
    Abstract: The disclosure discloses a method and device for monitoring partial discharge. The monitoring method including: step a, connecting a monitoring circuit in parallel to both ends of a tested product, disposing a ground wire between the monitoring circuit and ground, disposing a first sensor in the monitoring circuit, and disposing a ground wire sensor on the ground wire; step b, applying an excitation signal to the tested product, acquiring a first signal through the first sensor and acquiring a ground wire signal through the ground wire sensor within a monitoring cycle; and step c, determining whether the tested product has partial discharge through the first signal and the ground wire signal. The disclosure can avoid the partial discharge monitoring device from wrongly determining an interference signal to be a partial discharge signal, enhance anti-interference capability of the partial discharge monitoring device, and improve monitoring accuracy.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Lifeng Qiao, Dehui Zhang, Teng Liu