Abstract: The flow controller utilizes intelligent adapters to connect plural resources to a bus and a central arbiter that decides which adapters have access to the bus for the next bus cycle. Each adapter has an input buffer for transmitting data onto the bus, an output buffer for receiving data from the bus and a target register that identifies the destinations of the data in the input buffer. Each adapter communicates over control lines separate from the bus the following information: if its input buffer is nearly full, if its output buffer is either nearly empty or nearly full and the contents of its target register. The central arbiter gives highest priority to those adapters having nearly full input buffers with data for non-full output buffers, next highest priority to those adapters having nearly empty output buffers with data targeted by an input buffer and lowest priority to adapters with less than full input buffers having data for non-empty output buffers.