Abstract: Systems and methods for speculative execution of commands using a controller memory buffer are disclosed. Non-Volatile Memory Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on a host device placing commands into the submission queue and thereafter notifying a memory device of the commands placed in the submission queue. The submission queue may be resident in the memory device, such as in the controller buffer memory. Prior to notice by the host device, the memory device may determine that the commands have been placed in the submission queue and may speculatively execute the commands. Determining whether to begin processing a command prior to the host device notifying the memory device that the command is posted to the submission queue may be based on a type of command, such as a read or write command. The host device may override a command, such as a flush command, posted to the submission queue, and processing of the command canceled.

Abstract: An information processing apparatus includes a first memory and a processor coupled to the first memory. The processor is configured to acquire a first address in the first memory, at which an instruction included in a target program is stored. The processor is configured to simulate access to a second memory, such as a cache memory, corresponding to an access request for access to the first address on a basis of configuration information of the second memory. The processor is configured to generate first information, such as cache profile information, indicating whether the access to the second memory regarding the instruction is a hit or miss. The processor may be configured to acquire a number of cache misses for each of a plurality of pieces of arrangement information, and select a piece of arrangement information where the number of cache misses is smallest.

Abstract: A method includes identifying a state of an application and taking a snapshot of application data. The method continues to generate a virtual filter input/output snapshot from I/O filter records for the snapshot. The filer records are generated by a filter driver that intercepts I/Os between the application and disks that store application data. The method further includes releasing the snapshot, resuming the application and performing a backup using the virtual filter I/O snapshot. Finally, the method triggers the filter driver to replace multiple filter driver records corresponding to the virtual filter I/O snapshot with data indicating the application data was backed up using the virtual filter I/O snapshot.

Abstract: A cognitive hierarchical storage-management system receives feedback describing users' satisfaction with the way that one or more prior data-access requests were serviced. The system uses this feedback to associate each previously requested data element's metadata and storage tier with a level of user satisfaction, and to optimize user satisfaction when the system is trained. As feedback continues to be received, the system uses machine-learning methods to identify how closely specific metadata patterns correlate with certain levels of user satisfaction and with certain storage tiers. The system then uses the resulting associations when determining whether to migrate data associated with a particular metadata pattern to a different tier. Data elements may be migrated between different tiers when two metadata sets share metadata values. A user's degree of satisfaction may be encoded as a metadata element that may be used to train a neural network of a machine-learning module.

Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.

Abstract: A method for provisioning a volume of data is disclosed. The method involves identifying a set of rules associated with the volume of data, wherein the set of rules includes at least two conflicting rules, prioritizing the at least two conflicting rules, and placing the volume of data on a first computer system according to the prioritization. The method also includes collecting performance metrics corresponding to the placed volume of data, computing a score based on the collected performance metrics, determining if the computed score is acceptable, and determining that the placement is successful when the computer score is determined to be acceptable. The method further includes changing the prioritization of the at least two conflicting rules and placing the volume of data on a second computer system according to the changed prioritization when the score is determined to be unacceptable.

Abstract: A method and device for checking false sharing in deletion of a data block are disclosed. The method includes setting weight bits and a weight reset bit in a mapping pointer (MP) pointing to the data block, wherein the weight reset bit is configured to define whether a weight indicated by the weight bits has been increased; and determining, based on the weight bits and the weight reset bit, whether false sharing occurs. The method determines whether false sharing occurs accurately and with low cost by using a computable formula. All information for such computable formula comes from in-memory MP, with no need to load any extra metadata, for example, with no need to access Block Meta Data. The method also considers a scenario where a weight increase occurs during a weight split and merge with other pointers.

Abstract: An estimation method for read and write access performance adapted for a computer system including a host and a flash memory device is disclosed. The flash memory device includes a controller, and a flash memory module having a plurality of blocks. When the host transmits a writing performance query instruction, the controller executes a writing performance estimation process including determining whether at least one free block can accommodate data to be written. If Yes, a reply signal including an optimal writing performance is transmitted to the host; and if No, at least one block having data stored therein is selected for execution of a garbage collection process. When the host transmits a reading performance query instruction, the controller executes a reading performance estimation process including determining a threshold interval within which an average retry times of shift read is located to determine a corresponding estimated reading performance.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The data writing method includes transmitting a command to a host system to obtain a plurality of data, wherein the plurality of data are arranged in a sequence order in the host system, obtaining first data among the plurality of data and obtaining second data after obtaining the first data. The method further includes writing the first data to a corresponding physical page on a first word line among a plurality of word lines, and writing the second data to another corresponding physical page on a second word line among the plurality of word lines, wherein the first and second word lines belong to first and second memory sub-modules, and the first data and the second data are discontinuously arranged in the sequence order. The first and second data may each comprise sub-data, and the sub-data may be written into physical pages on the first and second word lines.

Abstract: A method comprises receiving input reference attributes from a data reference interface and selecting a replacement data location of a cache to store data. The replacement data location is selected based on the input reference attributes and reference states associated with cached-data stored in data locations of the cache and an order of state locations of a replacement stack storing the reference states. The reference states are based on reference attributes associated with the cached-data and can include a probability count. The order of state locations is based on the reference states and the reference attributes. In response to receiving some input reference attributes, reference states stored in the state locations can be modified and a second order of the state locations can be determined. A reference state can be stored in the replacement stack based on the second order.

Abstract: Systems, methods, and computer-readable media for intelligent distribution of data in a storage cluster are described herein. An example method includes maintaining a cluster volume table (CVT) that stores information regarding data distribution of a volume across a plurality of storage nodes, and defining data distribution groups within the CVT. The CVT includes a plurality of entries, where each entry identifies an owner storage node for a respective logical block of the volume. Each data distribution group includes consecutive CVT entries. The method also includes receiving an input/output (I/O) operation directed to a region of the volume, identifying an owner storage node associated with the region of the volume using the CVT, and serving the I/O operation with at least one storage node of a data distribution group associated with the owner storage node. The I/O operation is served at a chunk-level granularity that is finer than a logical-block-level granularity of the volume.

Abstract: An integrated circuit includes protected container access control logic to perform a set of access control checks and to determine whether to allow a device protected container module (DPCM) and an input and/or output (I/O) device to communicate securely through one of direct memory access (DMA) and memory-mapped input/output (MMIO). The DPCM and the I/O device are allowed to communicate securely if it is determined that at least the DPCM and the I/O device are mapped to one another, an access address associated with the communication resolves into a protected container memory, and a page of the protected container memory into which the access address resolves allows for the aforementioned one of DMA and MMIO. In some cases, a Security Attributes of Initiator (SAI) or security identifier may be used to obtain a DPCM identifier or attest that access is from a DPCM mapped to the I/O device.

Abstract: Methods and systems directed to a memory-side memory controller for interpreting capabilities and returning datasets to a Central Processing Unit (CPU) are provided. The CPU is configured to translate a first virtual address from a first capability to a first physical address, wherein the first capability is sent by a client application. The CPU is further configured to send the first physical address to the memory-side memory controller through a memory fabric. The memory-side memory controller loads a second capability located in the first physical address from an external memory through the memory fabric, interprets an address encoded within the second capability as a second physical address, and returns a dataset located in the second physical address from the external memory to the CPU through the memory fabric.

Abstract: An apparatus, method and machine-readable storage medium to improve memory access performance between shared local memory and system global memory are described. The method comprises grouping two or more work groups to form a super workgroup, and positioning a portion of a memory space into one or more super shared local memories (Super SLMs), wherein the memory space which is shared within the super workgroup forms at least one Super SLM of the one or more Super SLMs. The apparatus comprises: a plurality of execution units; a cache memory having a portion which operates as a shared local memory (SLM), which is shared with the plurality of execution units, at least one of which operates on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units operates on the different work groups.

Abstract: A computer-implemented method is provided, which includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, determining an anticipated throughput of each of the first and second data streams, assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream. Wear-leveling may be performed on open logical erase blocks, including assigning at least some open of the logical erase blocks to a queue. Open logical erase blocks having health values less than a health value of other logical erase blocks by a predetermined amount may be skipped over during the assigning of open logical erase blocks to the queue.

Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.

Abstract: A system, method and program product for exploiting in-storage transparent compression. A storage infrastructure is disclosed that includes: a storage device having physical block address (PBA) storage of a defined capacity, a transparent compression system that compresses data written to the PBA storage, and a logical block address-to-physical block address mapping table; and a host having a memory management system that includes: an initialization system that allocates an amount of logical block address (LBA) storage for the host having a capacity greater than the defined capacity of the PBA storage, and that creates a dummy file that consumes LBA storage without consuming any PBA storage; a system that gathers current PBA and LBA usage information.

Abstract: A method for maintaining I/O statistics in a tiered storage environment includes maintaining, by a tiered storage layer within a storage system, I/O statistics for data storage elements or areas within the storage system. The tiered storage layer migrates data between storage tiers in accordance with the I/O statistics. A data services layer, that operates independently from the tiered storage layer, alters (e.g., compresses, decompresses) selected data within the storage system and generates a message to the tiered storage layer describing the alteration. The message identifies the selected data, how the selected data before the alteration maps to the selected data after the alteration, and an operator (e.g., percentage) to be applied to I/O statistics associated with the selected data as a result of the alteration The tiered storage layer receives this message and modifies its internal I/O statistics accordingly. A corresponding system and computer program product are also disclosed.

Abstract: An apparatus and a method are provided. The apparatus of data analytics in a key-value solid state device (KVSSD) are disclosed. The KVSSD includes at least one KVSSD data container; and at least one KVSSD analytics container associated with at least one of the at least one KVSSD data container. The KVSSD data and analytics containers may be configured to store data and data analytics results in key-value pairs. The apparatus may include a virtual analytics container which is configured to utilize a field programmable gate array (FPGA) for performing a logical operation on data stored in multiple containers. A key in a key-value pair stored in a KVSSD analytics container may include a KVSSD data container identifier, a logical offset, and a user key that is also a key in a KVSSD data container associated with the KVSSD data container identifier. A value in a key-value pair may include a header of a fixed size, and analytics result information that depends on a type stored in the header.

Abstract: A data storage system comprises, a storage device having segments that are configured to store data, and storage logic coupled to the storage device that manages storage of data on the storage device using a translation table. The storage logic is executable to receive a first marker as part of a backup request, generate a second marker encapsulating a state of the storage device at a second time, calculate a difference between the first marker and the second marker, and generate a backup of data stored in the storage device based on the calculated difference between the first marker and the second marker. A garbage collection (GC) barrier may be set based on serial numbers associated with backup segments, and the garbage collection barrier may be incrementally released by releasing the garbage collection barrier for each segment after the segment has been backed up.