Abstract: A digital communication system comprises a transmitter for sequentially transmitting predetermined format data; and a plurality of receivers 102 each including a data selecting apparatus 104 for selecting required data from received data group and outputting selected data. The transmitter transmits data to the receivers in one of a first transmission mode having group destination directing information indicating that the data is to be transmitted to a receiving group consisting of predetermined receivers of the plurality of receivers, group specifying information for specifying a receiving group of receiving groups to which the data is to be transmitted, and in-group identification information for identifying a receiver in an arbitrary receiving group to which the data is to be transmitted, a second transmission mode having the group destination directing information and the group specifying information are included in the data, and a third transmission mode having the group destination directing information.

Abstract: A method and apparatus are disclosed for reducing the computational complexity of the RSSE technique. The apparatus and associated method does not assume that the signal energy of a pulse that has gone through a channel is always concentrated primarily in the initial taps, as is true for a minimum phase channel. The present invention, however, recognizes that the signal energy is often concentrated in just a few channel coefficients, with the remaining channel coefficients being close to zero. A receiver apparatus and associated method is disclosed for reducing the number of channel coefficients to be processed with a high complexity cancellation algorithm from L to V+K which contain the majority of the signal energy, while processing the L−(K+V) non-selected coefficients with a lower complexity algorithm. By only processing the intersymbol interference caused by a reduced number of channel coefficients (i.e.

Abstract: A plurality of communication signals is received. Each communication signal has an associated code. At least two of the communication signals has a different spreading factor. The associated codes have a scrambling code period. A total system response matrix has blocks. Each block has one dimension of a length M and another dimension of a length based on in part M and the spreading factor of each communication. M is based on the scrambling code period. Data of the received plurality of communication signals is received using the constructed system response matrix.

Abstract: In a frequency converter, a phase-locked loop generates a local-oscillation signal having a low frequency, of a plurality of local-oscillation signals having different frequencies, based on an intermediate frequency beacon signal that results from mixing a predetermined beacon signal with the local-oscillation frequency signal. Even if the phase-locked loop is used to generate the low frequency local-oscillation signal only, a frequency offset and a phase noise taking place in remaining high frequency local-oscillation signals are compensated for or canceled out. The frequency converter thus results in a high frequency accuracy. This arrangement reduces the number of bulky, costly and power-consuming phase-locked oscillators, typically used in the quasi millimeter band or the millimeter band. A simplified, compact frequency converter is thus provided, reducing both installation and operating costs.

Abstract: The method of differential communication for multiple transmitter antennas generalizes conventional coding of information in the phase shift between successive complex scalars signals used in single antenna communication to signals that are complex matrices. Each column of such a matrix represents a time sequence of signals emitted by a respective antenna of a multiple transmitter array. Preferably, the signal matrices are unitary matrices that form at least part of a finite group under multiplication. Data is encoded by making each transmitted signal the product of the previous signal and a selected one of the signal matrices.

Abstract: A communication system (20) employs fixed rate channel-optimized, trellis-coded quantization (COTCQ) at a plurality of diverse encoding bit rates. COTCQ is performed through a COTCQ encoder (40) and COTCQ decoder (54). The COTCQ encoder and decoder (40,54) each include a codebook table (62) having at least one codebook (64) for each encoding bit rate. Each codebook (64) is configured in response to the bit error probability of the channel (26) through which the communication system (20) communicates. The bit error probability influences codebooks through the calculation of channel transition probabilities for all combinations of codewords (90) receivable from the channel (26) given all combinations of codewords (90) transmittable through the channel (26). Channel transition probabilities are responsive to base channel transition probabilities and the hamming distances between indices for codewords within subsets of the transmittable and receivable codewords.

Abstract: A method (50) of operating a communications receiver (20). The method receives a communications signal (10) which is transmitted via a channel, where the communications signal comprises received known pilot data (DP) and received information data (DI), the known pilot data and information data being sequentially transmitted. The method then estimates a first channel impulse response (52) for the channel, wherein the first channel impulse response is in response to the received pilot data. Next, the method determines (54) a group of estimated information data in response to the first channel impulse response. Next, the method estimates a second channel impulse response (56) for the channel in response to the estimated information data. Thereafter, the method forms (56) a combined channel impulse response for the channel, using differing weights as applied to the first and second channel impulse responses.

Abstract: An asymmetric digital subscriber line transceiver unit-card (ATU-C) and a method of controlling the same. The ATU-C includes: a power supply unit; a plurality of modems to be connected to a plurality of asymmetric digital subscriber line transceiver unit-remote (ATU-R) for subscribers; a plurality of power switches for selectively supplying power generated by the power supply unit to the modems; and a microprocessor for controlling the operation of the power switches depending on the connection status between the subscribers and the modems.

Abstract: A method of compensating delay in an linearization loop of a power amplifier and a linearization arrangement of a power amplifier, which arrangement includes an I/Q modulator, one or more power amplifiers to be linearized and generating delay, and a feedback loop including an I/Q demodulator when the I/Q modulator and the I/Q demodulator derive an oscillator frequency from the same local oscillator. In accordance with the invention, the delay generated the power amplifier in the feedback is compensated by delaying a local oscillator signal applied to the I/Q demodulator. The delay of the local oscillator signal applied to the I/Q demodulator is generated by an amplifier optimized to have a great delay, preferably by a small-signal amplifier.

Abstract: A digital communication receiver includes a blind equalizer using the Constant Modulus Algorithm (CMA) to compensate for channel transmission distortion in digital communication systems. Improved CMA performance is obtained by using a partial trellis decoder to predict 1 bit or 2 bits of the corresponding 3-bit transmitted symbol. The predicted bits from the partial trellis decoder are used to reduce the effective number of symbols in the source alphabet, which reduces steady state jitter of the CMA algorithm. Specifically, the received input signal to the CMA error calculation is shifted up or down by a computed delta (&Dgr;), in accordance with the predicted bit(s). In addition, a different constant gamma (&ggr;), for the CMA error calculation is selected in accordance with the predicted bit(s).

Abstract: Methods and apparatus for implementing digital resampling circuits which create one or more bitstreams which include samples at desired rates, from an input bitstream having a fixed sample rate, are described. The resampling circuits of the present invention achieve the desired sample rates by performing digital interpolation on samples included in the input signal. The interpolation is performed using a filter, e.g., an all-pass infinite impulse response filter which produces an output as a function of a controllable signal delay.

Abstract: A synchronizer for providing a source-synchronized clock bus reduces the effect of clock skew during the signal capturing process. The synchronizer includes at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, and a multiplexer coupled to the at least one storage latch. The multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain. The signal is controlled and processed by strobe signals and clock signals from the sending chip.

Abstract: A direct conversion receiver which compensates for interfering signals introduced during processing. Direct conversion is achieved using direct detection techniques which introduce interfering signals which become inseparable from the wanted signal. A pilot signal (202) is added to an input RF signal (200) prior to passing the summed signal (206) to four separate paths (210, 212, 214, 216). Signal (206) is modulated so that the phase is different in each path using local oscillator signals and switches (230, 232, 234, 236), and then digitised by ADCs (260, 262, 264, 266). Correction is introduced into respective paths (210, 214) by cancellation loops (310, 314) to compensate for unwanted signals prior to the paths being grouped so that the pairs of digitised signals (272, 300; 276; 304) which are 180° out of phase with one another are subtracted to provide output inphase and quadrature signals (220, 224).

Abstract: In accordance with an aspect of the present invention, a circuit is provided which is configured to recover clock and data streams from an incoming signal. The circuit comprises a multiplexer having first and second inputs, and an output. The first input is configured to receive the incoming signal, and the second input is configured to receive a reference clock signal, while the output selectively supplies one of the incoming and reference clock signals. A toggling circuit, such as a flip-flop, and a frequency multiplier circuit are further provided which are coupled to the multiplexer output. A filter circuit is coupled to the frequency multiplier circuit, and the output of the filter circuit is coupled to a second input of the toggling circuit. Moreover, the output of the filtering circuit corresponds to the recovered clock stream, and an output of the toggling circuit corresponds to the recovered data stream.

Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: A signal generator and signal receiver, as well as method of signal generation and transmission, in which selected unstable periodic orbits of a lossy chaotic system are identified and extracted, and portions of the orbits concatenated together to form a resultant signal. The selected orbits are known to the signal detector a priori. The signal detector detects the transmitted signal by correlation of the received signal with the known extracted orbits, also allowing the detector identify information which the generator imposed onto the signal.

Abstract: An equalizer providing a filtered signal to a data decision unit calculates an amplitude error signal by comparing the filtered signal with the data signal output from the data decision unit, and calculates a squared envelope error signal from the filtered signal. These two error signals are separately weighted according to the absolute value of the amplitude error, the weight of the amplitude error signal decreasing and the weight of the squared envelope error signal increasing as the absolute value of the amplitude error increases. The weighted amplitude error signal and weighted squared envelope error signal are added to obtain an error signal used in updating filter coefficients in the equalizer. Rapid convergence of the filter coefficients is obtained, with small residual error.

Abstract: An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.

Abstract: A signal converting device and method for converting signals from memory interfaces into main system interfaces. The present invention can completely convert response signals from high frequency devices into low frequency devices, for solving low efficient and disadvantages caused by asynchronous conversion. The signal loss is not occurred when the signal converting device is in pseudo synchronization. By applying the present invention, the computer system can work normally and rapidly, in which the frequency of the request signals from the main system interface is higher than half of the frequency of the response signals from the memory interface. The compurter system is, for example computer system for 100 MHz/133 MHz or 66 MHz/100 MHz.