Abstract: According to one embodiment, a method of processing broadcast data in a broadcast transmitter includes: encoding the broadcast data for broadcast service; encoding signaling information for signaling the broadcast data; assigning the encoded broadcast data and the encoded signaling information into a signal frame; and transmitting a broadcast signal including the signal frame. The broadcast signal further includes a signaling table having access information of the broadcast data. The signaling table includes service id information for identifying the broadcast service and component information for indicating a number of components in the broadcast service.

Abstract: Techniques for encoding data storage systems using grid encoded data storage systems are described herein. Data to be stored in a data storage system is obtained and the data is stored in a grid of shards using grid encoding techniques that store the data in a combination of data shards and derived shards. Each of the shards has at least a first index corresponding to one dimension of the grid and a second index corresponding to a second dimension of the grid. Loss of a plurality of data shards can be repaired because each shard is reproducible from one or more shards with a first index that is associated with the first index of the shard and is also reproducible from one or more shards with a second index that is associated with the second index of the shard.

Abstract: A computer program product, system, and method for generating and storing a parity chunk using at least a first chunk and a second chunk; detecting at least one unused segment within the first chunk; generating a new chunk as a third chunk; associating one or more used segments from the first chunk to the third chunk; filling an unused segment within the third chunk with new data; calculating a delta parity between the first chunk and the third chunk; and updating the stored parity chunk using the delta parity.

Abstract: A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.

Abstract: Disclosed are a fault-localization and error-correction method for a self-checking binary signed-digit adder and a digital logic circuit for performing the method. More specifically, a fault-localization and error-correction method for a self-checking binary signed-digit adder in which a stuck-at fault of the self-checking binary signed-digit adder may be detected at low cost and with low complexity and in which an error may be autonomously corrected using the self-dual concept, and a digital logic circuit for performing the method are disclosed.

Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N?K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q?K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q?K frozen bits are allocated to the N?K frozen bit-channels and the q additional frozen bit-channels.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and to the memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device determines storage unit (SU)-based write transfer rates and/or a DSN-based write transfer rate for a write request of encoded data slices (EDSs) to the SUs within the DSN. Then, the computing device processes the SU-based write transfer rates and/or DSN-based write transfer rate to determine characteristics of the various SUs as well as operation of the DSN. The computing device then selectively modifies parameters (e.g., write request time interval) and/or issues additional write request(s) for some or all of the EDSs based on such characteristics.

Abstract: Systems and methods presented herein enhance WiFi communications in a RF band where conflicting LTE signaling exists. In one embodiment, a system includes a processor operable to detect the WiFi communications between a UE and a wireless access point of a WiFi network, to identify errors in the WiFi communications, and to determine a periodicity of the errors based on the LTE signaling structure. The system also includes an encoder communicatively coupled to the processor and operable to encode the WiFi communications with error correction, and to change the error correction based on the periodicity of the errors in the WiFi communications.

Abstract: Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may have a plurality of bits stored in multi-level memory cells. The method may include identifying one or more errors in a plurality of memory cells. The method may further include converting the erroneous cells to erasures. The method may further include correcting the one or more erasures.

Abstract: Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Abstract: A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.

Abstract: The present invention relates to a method and encoding device for encoding a sequence of m-bit pattern words and outputting as a bit-stream a frame comprising corresponding n-bit symbols as well as a predetermined comma symbol, wherein m<n, wherein occurrences of false commas in the output bitstream are avoided. The output bitstream may further be optimized based on CID count and DC balance.

Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.

Abstract: A method and system are disclosed for providing integrated circuit chip cards (e.g. transaction cards) pursuant to an order placed by or on behalf of a card issuer wherein a testing data file is provided in conjunction with prepersonalization data encoding for use in conjunction with subsequent testing of the accuracy of the encoded prepersonalization data. Such testing may be completed prior to personalization data encoding to facilitate the identification of prepersonalization data encoding errors, thereby further facilitating remedial action and reduction of production disruptions.

Abstract: A method includes a first computing device retrieving a decode threshold number of encrypted encoded data slices. The method further includes the first computing device generating a decoding matrix based on pillar numbers of the decode threshold number of encrypted encoded data slices and an encoding matrix. The method further includes the first computing device dispersed storage error decoding the decode threshold number of encrypted encoded data slices based on the decoding matrix to produce an encrypted data segment. The method further includes the first computing device sending the encrypted data segment and the pillar numbers to a second computing device. The method further includes the second computing device identifying a particular subset of encryption keys of the set of encryption keys based on the pillar numbers. The method further includes the second computing device decrypting the encrypted data segment based on the particular subset of encryption keys.

Abstract: Techniques for incrementally updating grid encoding data storage systems are described herein. A grid of shards with a plurality of virtual shards is created where each virtual shard is a representation of a shard in the grid of shards that is not backed by a data storage device and where each shard of the grid of shards has an index value. Data is then stored in the grid of shards by updating a shard to store the data and by also updating a second shard based on a set of shards with the same index value as the shard updated to store the data.

Abstract: A memory controller 2 of a memory system 1 according to an embodiment is provided with an encoding device 10 and a memory interface 5. The encoding device 10 is provided with an encoder 15 which generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaver 111 which sequentially interleaves the plurality of user data, and an XOR accumulator 112 which sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encoder 15 generates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interface 5 writes a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory 9.

Abstract: Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.