Abstract: A sensing system includes a plurality of probes arranged in a spaced relation around a stage that is adapted to support a substrate. Each probe includes a detection portion adapted to move from a known starting position toward an edge of the substrate that is supported by the stage; detect the edge of the substrate while the substrate is supported by the stage; generate a detection signal following said detection; and stop moving toward the edge of the substrate following said detection. A controller may determine an edge position of the substrate relative to the stage based on the known starting position of each detection portion and based on the detection signal generated by each detection portion. Numerous other aspects are provided.

Abstract: A probe navigation method, a navigation device, and a defect inspection device wherein in a charged particle beam system provided with probes for electrical characteristics evaluation, probing can be easily carried out regardless of the equipment user's level of skill are provided. To attain this object, probes and a test piece stage on which a test piece is placed are driven by independent driving means. Further, a large stage driving means which integrally drives the probes and the test piece stage is provided. In addition, CAD navigation is adopted. This enhances the equipment users' convenience during probing.

Abstract: A probe card assembly can comprise a support structure to which a plurality of probes can be directly or indirectly attached. The probes can be disposed to contact an electronic device to be tested. The probe card assembly can further comprise actuators, which can be configured to change selectively an attitude of the support structure with respect to a reference structure. The probe card assembly can also comprise a plurality of lockable compliant structures. While unlocked, the lockable compliant structures can allow the support structure to move with respect to the reference structure. While locked, however, the compliant structures can provide mechanical resistance to movement of the support structure with respect to the reference structure.

Abstract: An avalanche test circuit for applying an avalanche test signal to a device under test, comprising a series combination of a voltage source and an inductance; a switching device connected in parallel with said series combination; a diode for being connected to a test terminal of said device under test, said diode being connected to a connection point of said inductance and said switching device; a common terminal of said device under test being connected to a connection point of said switching device and said voltage source.

Abstract: There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range. Accordingly, the validity of the signal outputted from the device can be measured without any expensive external measuring device. Also, when the test must be done before the packaging stage, the test can be simply performed, thereby reducing the test cost greatly.

Abstract: A system and method for testing standby current of a semiconductor package is provided. The method includes testing semiconductor chips formed on a wafer having a predetermined wafer run number, collecting measured values of standby current of the semiconductor chips, and storing the measured values of standby current in a database, by using a wafer tester; recognizing a wafer run number of each of semiconductor packages to be tested; downloading measured values of standby current of semiconductor chips corresponding to the recognized wafer run number from the database to a semiconductor package tester; extracting a boundary value defining predetermined upper values of the downloaded measured values of standby current, by using the semiconductor package tester; setting the boundary value as a standby current limit of a program for testing the semiconductor packages by use of the semiconductor package tester; and testing the semiconductor packages based on the standby current limit.

Abstract: The present invention is for enabling to carry out probing tests en bloc at the same time on electronic devices and semiconductor chips having high-density terminals. For this purpose, the electric signal connecting device includes vertical probes for getting into contact with terminals for electric connection created on electric functional elements to be tested for electric connection, and a resin film supporting the vertical probes, and the vertical probes are planted resiliently deformably in a surface of a resin film in a direction along the film surface, and an end of the vertical probes is brought into contact with terminals of electric functional elements to be tested and another end of the vertical probes is brought into contact with terminals of an electric function testing apparatus so that signals may be transmitted and received between the electric functional elements to be tested and the electric function testing apparatus.

Abstract: A vertical-type probe card includes a circuit board, which has signal circuits and grounding circuits arranged in such a manner that each signal circuit is disposed in parallel and adjacent to one grounding circuit and kept a predetermined distance from the grounding circuit, and a probe assembly, which is arranged at the bottom side of the circuit board and has an upper guide plate, a lower guide plate, a conducting layer provided on the lower guide plate, a plurality of signal probes respectively electrically connected to the signal circuits and adjacent to a plurality of compensation probes, and at least one grounding probe electrically connected to the grounding circuits in a manner that the signal, compensation and grounding probes are vertically inserted through the upper and lower guide plates, and the conducting layer is conducted with the compensation probe and the grounding probe while electrically insulated to the signal probe.

Abstract: An improved method and apparatus for automatically and accurately aligning a wafer prober to the bonding pads of a semiconductor device are provided. In one embodiment of one aspect of the invention, a multi-loop feedback control system incorporating information from a number of sensors is used to maintain the desired contact position in the presence of disturbances. Other aspects and other embodiments are also described.

Abstract: A test probe having a conductive part electrically connected to terminals of a test-object device, including: a silicon substrate; a protrusion made of resin provided on the silicon substrate; a first conductive part which is provided on the protrusion and comes in contact with the terminals; and a second conductive part which is provided in a region other than a region having the protrusion on the silicon substrate and is electrically connected to the first conductive part.

Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.

Abstract: An integrated circuit includes a current generator circuit with a first input terminal for applying a reference voltage and a second input terminal for applying an input voltage, which is generated internally from an externally applied supply voltage by a voltage generator circuit. The current generator circuit is connected to an output terminal via an interconnect. A first current flows on the interconnect in a test operating state of the integrated circuit. The current generator circuit generates a first partial current in a first test cycle of a test operating state and a second partial current in a subsequent second test cycle. The partial currents are each superposed on the first current on the interconnect. Consequently, three currents occur at the output terminal during the test operating state. The internally generated input voltage of the current generator circuit is determined from the three currents and the reference voltage.

Abstract: A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Abstract: An apparatus and a method testing liquid crystal display panel which are able to test whether or not burr remains on longer sides and on shorter sides of a unit liquid crystal display panel using first to fourth testing bars in a touch method, and able to measure a distance between the longer sides and a distance between the shorter sides of the unit liquid crystal display panel.

Abstract: A power MOSFET, comprising main and current mirror MOSFETs, has a current sense resistance coupled between its mirror and source terminals and a monitoring circuit responsive to a first voltage dependent upon current through the current sense resistance. The circuit arrangement includes a circuit that determines a second voltage, different from the first voltage, of a terminal of the current mirror MOSFET, and a circuit arranged to determine current of the power MOSFET in dependence upon the first and second voltages. The second voltage can be the voltage at the drain terminal, or the voltage at the mirror terminal with switching of the current sense resistance or a current that it passes. It can alternatively be determined by a control circuit to be a desired fraction of the drain voltage.

Abstract: A fault detection apparatus for surface mount packages is provided. The apparatus can include a retainer for releasably securing a circuit board such as a printed circuit board having an electrical component mounted thereon via a ball grid array surface mount package. When mounted within the apparatus, a test signal is applied to the electrical component. The apparatus includes a mechanical actuator, such as a solenoid, for applying a reciprocating force to the circuit board. The reciprocating force can disturb a defect in the ball grid array manifesting as a mechanically unreliable connection at one of the balls where an electrically intermittent connection is occurring. By disturbing the mechanically unreliable connection, the electrically intermittent connection can be caused to fail altogether and thereby reveal the defect as a test signal is carried through the printed circuit board.

Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A current sensor includes coupled inductors that generate an output current responsive to a detected current. The coupled inductor is implemented in an integrated circuit. An integrator circuit generates a sensed voltage responsive to the output current.

Abstract: An inspection apparatus for a TFT substrate formed with a plurality of pixels, includes a reference substrate being opposite to and spaced from the TFT substrate and formed with a plurality of reference patterns corresponding to the pixels, a power supply to supply power to both a predetermined number of the pixels and the corresponding reference pattern to form an electric field in a space between the TFT substrate and the reference substrate, an electron beam emitter to emit an electron beam to travel from a first side to a second side of the space, an electron beam detector to detect the electron beam emitted from the electron beam emitter and passed through the space, and a controller to determine whether the TFT substrate includes a defective pixel based on a location of the electron beam detected by the electron beam detector. Thus, the inspection apparatus can correctly and quickly inspect the TFT substrate for defects in a low vacuum state regardless a size of the TFT substrate.