Abstract: A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically.

Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, the storage device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable storage media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A local volatile memory has separate HDD and SSD partitions respectively accessible by the HDD and SSD controller circuits. A top level controller circuit performs a cleaning operation to transfer a data set from the non-volatile solid state memory to the rotatable storage media by issuing a read command to the HDD controller circuit to retrieve the data set to the HDD partition, transferring the data set from the HDD partition to the SSD partition, and issuing a write command to the SSD controller circuit to write the data set from the SSD partition to the non-volatile solid state memory.

Abstract: A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.

Abstract: Systems and methods for notifying one or more observers of one or more state changes are provided. For instance, at least one subject can be configured to write data to a buffer in a shared memory space. One or more observers can have an associated notification group that includes one or more buffer identifiers corresponding to a buffer in the shared memory space. A scheduler can be configured to detect one or more state changes associated with one or more buffers in the shared memory space and to provide an update notification to at least one observer based at least in part on the one or more detected state changes.

Abstract: A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.

Abstract: Systems and methods for performing operations on memory of a computing device are disclosed. According to an aspect, a method includes storing update data on a first memory of a computing device, wherein the update data comprises data for updating a second memory on the computing device. The method also includes initiating an update mode on the second memory. Further, the method includes suspending an I/O operation of the second memory. The method also includes switching the computing device to a system management mode (SMM) while the second memory is in the update mode. Further, the method includes retrieving the update data from the first memory. The method also includes determining whether the update data is valid. The method also includes resuming the I/O operation of the second memory for updating the second memory based on the retrieved update data in response to determining that the update data is valid.

Abstract: A system for estimating a quantity of unique identifiers comprises a processor and a memory. The processor is configured to, for each of k times, associate a bin of a set of bins with each received identifier. The processor is further configured to determine an estimate of the quantity of unique identifiers based at least in part on an average minimum associated bin value. The memory is coupled to the processor and configured to provide the processor with instructions.

Abstract: A nonvolatile memory device includes user blocks and reserved blocks. A ratio of the number of used reserved blocks among the reserved blocks during a predetermined period to an operation count during the predetermined period is calculated by a memory controller and an end of lifetime warning signal is transmitted to an external device based on the calculated ratio. Bad blocks among the user blocks are replaced by one or more of the reserved blocks. If at least one block among the user blocks becomes a bad block, the memory controller replaces the bad block with any one of the reserved blocks, and the reserved block used indicates a reserved block replaced with at least one of the user blocks. The operation count can be an erase count or a program count of the nonvolatile memory device, or a time count indicating usage time.

Abstract: Data transfer between processors is efficiently performed in a multiprocessor including a shared cache memory. Each entry in a tag storage section 220 of a cache memory holds a reference number field 224 in addition to a tag address field 221, a valid field 222, and a dirty field 223. The reference number field 224 is set in a data write, and the value thereof is decremented after each read access. When the value of the reference number field 224 is changed from “1” to “0”, the entry is invalidated without performing a write-back operation. When the cache memory is used for communication between processors in the multiprocessor system, the cache memory functions as a shared FIFO, and used data is automatically deleted.

Abstract: A storage cluster is provided. The storage cluster includes a plurality of storage nodes coupled together as the storage cluster. The plurality of storage nodes is configured to assign data to two or more logical arrays and the plurality of storage nodes is configured to establish data striping across the plurality of storage nodes for user data of each of the two or more logical arrays.

Abstract: A system and method of operation exploit the limited associativity of a single cache set to force observable cache evictions and discover conflicts. Loads are issued to input memory addresses, one at a time, until a cache eviction is detected. After observing a cache eviction on a load from an address, that address is added to a data structure representing the current conflict set. The cache is then flushed, and loads are issued to all addresses in the current conflict set, so that all known conflicting addresses are accessed first, ensuring that the next cache miss will occur on a different conflicting address. The process is repeated, issuing loads from all input memory addresses, incrementally finding conflicting addresses, one by one. Memory addresses that conflict in the cache belong to the same partition, whereas memory addresses belonging to different partitions do not conflict.

Abstract: In one embodiment, a computer-implemented method includes producing one or more clean frames by clearing a batch of one or more frames for use in backing virtual memory pages. The producing the one or more clean frames may be performed asynchronously from a unit of work being performed by a processor. The one or more clean frames may be added to a clean frame queue, where the clean frame queue includes a plurality of clean frames that have been cleared. A first request may be received, from the processor, for a frame for use in backing a virtual memory page of the unit of work. A clean frame, of the one or more clean frames, may be removed from the clean frame queue, responsive to the first request. The clean frame may be delivered to the processor, responsive to the first request.

Abstract: A data storage device includes a controller, a non-volatile memory, and a buffer accessible to the controller. The buffer is configured to store data retrieved from the non-volatile memory to be accessible to a host device in response to receiving from the host device one or more requests for read access to the non-volatile memory while the data storage device is operatively coupled to the host device. The controller is configured to read an indicator of cached data in response to receiving a request for read access to the non-volatile memory. The request includes a data identifier. In response to the indicator of cached data not indicating that data corresponding to the data identifier is in the buffer, the controller is configured to retrieve data corresponding to the data identifier as well as additional data from the non-volatile memory and to write the data corresponding to the data identifier and the additional data to the buffer.

Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.

Abstract: Embodiments disclosed in the detailed description include hybrid write-through/write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-hack cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

Abstract: The invention relates to any electronic device such as a chip card, a passport, a dongle or any other object requiring personalization of the content of a memory. More precisely, the invention provides for a method for processing a data item of a container stored in a memory, said method being implemented by the electronic device by utilizing in particular a table of identifiers. The invention furthermore provides for a prior step for associating a data identifier with a data item of a container and creating said table of identifiers.

Abstract: A circuit comprises a data storage element that includes a sampling stage configured to sample a data value, the sampling stage comprising a plurality of p-type devices, wherein at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices, a plurality of n-type devices, wherein at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices, a feedback stage configured to maintain the data value sampled by the sampling stage.

Abstract: An initial remote region of a first remote storage device of a remote storage system not matching a corresponding local region of a local storage device of a remote local system is detected. A subsequent remote region on the remote storage system—matching the initial remote region is identified. Data in the initial remote region is replaced with data from the subsequent remote region.

Abstract: An initial remote region of a first remote storage device of a remote storage system not matching a corresponding local region of a local storage device of a remote local system is detected. A subsequent remote region on the remote storage system matching the initial remote region is identified. Data in the initial remote region is replaced with data from the subsequent remote region.

Abstract: A system and method of improved storage request handling in host-side caches includes a host-side cache with a cache controller, a plurality of request queues, and a cache memory. The cache controller is configured to receive a storage request, assign a priority to the storage request based on a queuing policy, insert the storage request into a first request queue selected from the plurality of request queues based on the assigned priority, extract the storage request from the first request queue when the storage request is a next storage request to fulfill based on the assigned priority, forward the storage request to a storage controller, and receive a response to the storage request from the storage controller. The queuing policy is implemented using a rule-based policy engine. In some embodiments, the cache controller is further configured to update one or more monitoring metrics based on processing of the storage request.