Abstract: An apparatus comprising an interface, a light projector and a processor. The interface may be configured to receive pixel data. The light projector may be configured to generate a structured light pattern. The processor may be configured to process the pixel data arranged as video frames and generate disparity and depth maps. The processor may comprise convolutional neural network hardware that may arrange reference images into a tensor, perform logical operations on one of the video frames in a depth direction of the tensor to generate a tensor of feature maps of the video frames, use a convolution to reduce an amount of calculations performed in the depth direction of the tensor of feature maps, perform convolution filtering on the tensor of the feature maps, determine an index map location, and search lookup data based on the index map location to determine the disparity and depth maps.

Abstract: This disclosure relates generally to estimating age of a leaf using morphological features extracted from segmented leaves. Traditionally, leaf age estimation requires a single leaf to be plucked from the plant and its image to be captured in a controlled environment. The method and system of the present disclosure obviates these needs and enables obtaining one or more full leaves from images captured in an uncontrolled environment. The method comprises segmenting the image to identify veins of the leaves that further enable obtaining the full leaves. The obtained leaves further enable identifying an associated plant species. The method also discloses some morphological features which are fed to a pre-trained multivariable linear regression model to estimate age of every leaf. The estimated leaf age finds application in estimation of multiple plant characteristics like photosynthetic rate, transpiration, nitrogen content and health of the plants.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.

Abstract: A DMA computer system (10) for driving a peripheral device such as an LCD display (12) of a GPS receiver without stealing excessive cycles from a CPU (18). The DMA computer system (10) includes a CPU (18), a first memory (20) that may be written to or read by the CPU (18), a second memory (22) that may be written to or read by the CPU (18), and a DMA controller (24) coupled with the CPU (18) and the second memory (22). The DMA controller (24) is operable to: read data from the second memory (22) and transfer the data to the peripheral device; delay the CPU (18) from accessing the second memory (22) while the DMA controller (24) is reading data from the second memory (22); enable the CPU (18) to regain access to the second memory (22) once the DMA controller (24) has finished reading data from the second memory (22); and allow the CPU (18) to access the first memory (20) without delay even while the DMA controller (24) is reading data from the second memory (22).

Abstract: A video graphics system that includes a graphics processing circuit and a logic enhanced memory is presented. The logic enhanced memory includes an operation block that performs blending operations for fragment blocks received from the graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. In order to allow limited bandwidth buses that transport data between the graphics processing circuit and the logic enhanced memory to be used with maximum efficiency, an input buffer and an output buffer are included in the logic enhanced memory. A graphics processing circuit maintains history data that indicates how full the input and output buffers of the logic enhanced memory are, and as such, can ensure that new fragments blocks and operational commands are not provided to the logic enhanced memory in a manner that would cause the processing capabilities of the logic enhanced memory to be exceeded.