Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the memory controller circuit includes a row buffer, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

Abstract: Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.

Abstract: A memory device includes a plurality of arrays coupled in parallel with each other. A first array of the plurality of arrays includes a first switch and a plurality of first memory cells that are arranged in a first column, a second switch and a plurality of second memory cells that are arranged in a second column, and at least one data line coupled to the plurality of first memory cells and the plurality of second memory cells. The second switch is configured to output a data signal from the at least one data line to a sense amplifier.

Abstract: Systems and methods for controlling a peripheral device with a web browser. A system includes a peripheral device and a user computing device executing a web browser and a device manager, the device manager configured to operate the peripheral device and including a device manager web server. An authentication token can be passed to the web browser from a web server upon coupling of the peripheral device with the user computing device and login by the user with the web browser. The web browser can pass the authentication token to the device manager through the device manager web server. The device manager can transmit the authentication token to the web server to pair the web browser with the device manager.

Abstract: A method for distributed application distribution may include: (1) receiving, at a first decentralized marketplace instance in a distributed ledger network and from a first node of the plurality of nodes, the first node associated with a distributed application creator, a distributed application; (2) making available, by the first decentralized marketplace instance, the distributed application to decentralized marketplace instances, wherein the first node is configured to provide the distributed application to a second node, the second node associated with a distributed application collaborator; (3) receiving, at a second decentralized marketplace instance and from the second node, a modified version of the distributed application; and (4) making available, by the second decentralized marketplace instance, the modified version of the distributed application to the decentralized marketplace instances, wherein the second node is configured to provide the distributed application to a third node, the third node a

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

Abstract: Systems and methods are provided for provisioning identity credentials based on interactions with verified or trusted users. One exemplary computer-implemented method includes receiving a request for a digital identity from a user, where the request includes identifying information for the user and a verified user identifier, and transmitting, to a verified user associated with the verified user identifier, an attestation request for the user. The method also includes receiving, from the verified user, an attestation in response to the attestation request with regard to at least some of the identifying information for the user, generating a digital identity for the user based on a number of attestations of the identifying information for the user, and sharing a digital identity notice with the user including an identifier for the user, whereby the user is permitted to share the digital identity with a relying party via the identifier.

Abstract: A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Abstract: A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.

Abstract: An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

Abstract: Systems and methods for obfuscating and/or deleting data records are provided. In one implementation, a method for obfuscating data includes a step of receiving a request from a client to obfuscate data records associated with the client. The data records are stored in one or more databases throughout a network. The method also includes searching for one or more occurrences of the data records appearing throughout the network. Upon determining that the data records can be obfuscated without causing undesirable consequences elsewhere in the network, the method includes obfuscating the one or more occurrences of the data records.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: Methods, systems, and devices for techniques for memory cell refresh are described. A memory system may support a low power mode in which the memory system may periodically perform a refresh operation. In some cases, the memory system and a host system coupled with the memory system may support a command to enter the low power mode. As part of the low power mode, the memory system may receive at least one power supply of one or more supported power supplies, such that the memory system may remain active and thus periodically perform the refresh operation. In some cases, the memory system may adjust the periodicity of the refresh operation in response to detecting a triggering event, such as a high temperature, a large system age, or a combination thereof.

Abstract: A file protection method of a computer apparatus including a processor, the method including extracting classes from an executable file of a package file, classifying the classes into class groups, adding a loading code to a first class group among the class groups, the loading code configured to cause sequential loading of the class groups to a memory in a random loading order in response to execution of the package file, adding an integrity code to a second class group among the class groups, the integrity code configured to verify an integrity of a corresponding class group among the class groups or a previous class group among the class groups, the previous class group including the loading code configured to cause the corresponding class group to load, and regenerating the package file using the class groups after the adding the loading code and the adding the integrity code.

Abstract: Inter-chip communication data in an Internet-of-Things (IoT) device is manipulated and analyzed to identify and remediate security vulnerabilities. Inter-chip communication data in the IoT device is captured. Communication direction, address format, flow control, communication timing, and communication structure associated with the inter-chip communication data is identified. Based on the foregoing identification(s), portions of the inter-chip communication data that require modification are identified so that that inter-chip communication data can be replayed. Based on the modification and the replaying, security vulnerabilities in the IoT device are identified and remediated.

Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Abstract: A memory system including a plurality of memory cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The plurality of memory cells are arranged in rows and columns, each of the plurality of memory cells having a gate, a drain, and a source. In the plurality of word lines, each of the word lines having a corresponding row, wherein each of the word lines is coupled to the gates of the memory cells in the corresponding row. In the plurality of bit lines and the plurality of source lines, each of the bit lines and each of the source lines having a corresponding column, where each of the bit lines is connected to the drain of the memory cells in the corresponding column and each of the source lines is connected to the source of the memory cells in the corresponding column.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W? values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)?(W?).

Abstract: A nonvolatile memory device includes an array of magnetic memory cells, and control logic circuit having a voltage generator therein, which is configured to generate a gate voltage. A row decoder is provided, which is connected by word lines to the array of magnetic memory cells, and has a word line driver driven therein, which is responsive to the gate voltage. A column decoder is provided, which is connected by bit lines and source lines to the array of magnetic memory cells. A write driver is provided, which has a write voltage generating circuit therein that is configured to output a write voltage, in response to: (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which a write operation is to be performed.