Abstract: A first control apparatus includes a first memory unit including a local cache, a first power supply that supplies electric power to the first memory unit, and a control unit. The control unit controls a write into a memory device by a write-back method, using the local cache. The control unit mirrors data of the local cache in a mirror cache of a second control apparatus. The control unit determines whether the mirror cache is included in a second memory unit that receives electric power from a second power supply of the second control apparatus, upon detecting an abnormal state of a battery for supplying electric power to the second memory unit in case of power outage of the second power supply. The second memory unit switches write control for the memory device to a write-through method, when the second memory unit includes the mirror cache.

Abstract: A directory maintenance method and apparatus are provided. The method includes sending, by a main memory according to a correspondence between a cache line in a directory and a cache, listening information to each cache corresponding to a cache line at a preset frequency; receiving, by each cache corresponding to the cache line, the listening information, and sending a listening response according to the listening information; and receiving, by the main memory, the listening response, and updating the directory according to the listening response, where the listening response includes a state of the cache line in the cache sending the listening response. The directory maintenance method and apparatus that are disclosed in the present invention can lower an impact of listening caused due to replacement on normal processing of a processor, and reduce degradation of system performance.

Abstract: A system and method for consolidating a plurality of heterogeneous storage systems in a data center comprising collecting data from a plurality of heterogeneous storage devices using data collection tools, using Data Preparation Tool for extracting and translating the collected data, populating a Data Model stored in source storage configuration unit suitable for analysis, analyzing and classifying the collected data by an analysis unit based upon a plurality of attributes, comprising of a Consolidation Advisor that uses the analyzed data and candidate Target System Configurations, Preferences & Constraints for generating optimum number, specification & configuration of the Consolidate Target State infrastructure and mappings of logical units from as-is data center storage infrastructure to the target state, and iteratively validating the same in a Validation task till the final desired consolidation and objectives are met.

Abstract: A storage system includes a plurality of storage devices, each including a storage medium and a compression function for data, and a storage controller coupled to the plurality of storage devices. The storage controller includes compression necessity information indicating necessity of compression of the data in a write command to be transmitted to a storage device at a write destination among the plurality of storage devices. The storage device at the write destination writes, when the compression necessity information included in the received write command indicates that compression is unnecessary, the data in the storage medium without compressing the data.

Abstract: Exemplary embodiments provide subsidiary volume management. In one embodiment, a storage system comprises: a memory being operable to store information of a plurality of logical unit groups, each of the plurality of logical unit groups including information of an administrative logical unit (LU) and information of one or more subsidiary LUs to be accessed from a virtual machine on a computer; and a controller being operable to create or select an administrative LU and to inform the computer of the created or selected administrative LU according to evaluation of a subsidiary LU which relates to another administrative LU, when the controller receives a command from the computer to said another administrative LU.

Abstract: A Flash Translation Layer (FTL) structure including mapping information for storing data is disclosed. The FTL structure includes a plurality of hierarchical data groups including a zeroth-layer host data group, and first-layer to nth-layer metadata groups, and zeroth to nth logs configured in a hierarchical structure in correspondence with the respective hierarchical data groups, for processing data of the corresponding data groups. A kth log (0?k?n) provides an interface to volatile memory resources dividedly allocated to the kth log, an interface to non-volatile memory resources dividedly allocated to the kth log, and an interface to at least one of (k?1)th and (k+1)th logs.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

Abstract: The present invention provides a method for managing memory space in an electronic device including: selecting a candidate page from a first memory space for swapping the candidate page out of the first memory space into the second memory space; compressing the candidate page to obtain a first compressed page and a first hash value of the first compressed page; performing a comparison using the first hash value of the first compressed page and the hash values of the pages stored in a second memory space to find whether the pages have the same content as the first compressed page or the candidate page; and if a page is found to have the same content as the first compressed page or the candidate page, mapping a virtual address of the first compressed page or the candidate page to the found page.

Abstract: Methods for protecting data on an integrated circuit including a memory are described. One method includes storing nonvolatile protection codes on the integrated circuit. The nonvolatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in a plurality of sectors of the memory. The method includes storing volatile protection codes on the integrated circuit. The volatile protection codes have a first value indicating a protected state or a second value indicating an unprotected state for respective sectors in the plurality of sectors. The method includes blocking modification in a particular sector using circuitry on the integrated circuit when the volatile protection code for the particular sector has the first value, else allowing modification in the particular sector, and setting the volatile protection codes to values of the nonvolatile protection codes in an initialization procedure.

Abstract: A method of allocating data to a storage block included in a storage network may include determining a plurality of characteristics associated with a storage block included in a storage network. The plurality of characteristics may include storage capacity of the storage block, available storage space of the storage block, likelihood of loss of data stored on the storage block, availability of the storage block with respect to the storage network, and use of the storage block. The method may further include allocating data to the storage block based on the plurality of characteristics.

Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register.

Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.

Abstract: A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.

Abstract: Systems and methods are disclosed for accessing data over a distributed data storage network. A network-attached storage device (NAS) includes a non-volatile memory module comprising a first portion of data storage for storing local user data associated with a host computing device and a second shared portion of data storage for storing third-party data. The NAS includes a controller configured to provide copies of a portion of the user data to one or more other NAS's for storage therein, receive third-party data from each of the one or more other NAS's, and store the received third-party data in the second portion of data storage. The NAS is configured to upload at least a portion of the user data to the host computing device and upload at least a portion of the third-party data to at least one of the one or more other NAS.

Abstract: A cross-page prefetching method, apparatus, and system are disclosed, which can improve a prefetching hit ratio of a prefetching device, and further improve efficiency of memory access. The method includes: receiving an indication message, sent by a cache, that a physical address is missing, where the indication message carries a mapped-to first physical address and contiguity information of a first physical page to which the first physical address belongs; acquiring a prefetching address according to the first physical address and a step size that is stored in a prefetching device; and if a page number of a physical page to which the prefetching address belongs is different from a page number of the first physical page, and it is determined, according to the contiguity information of the first physical page, that the first physical page is contiguous, prefetching data at the prefetching address.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A storage management system monitors relationships between data sets stored on current implementation resources, such as a storage servers. The relationships may be used to determine whether a data set should be moved from a current implementation resource to an available implementation resource.

Abstract: In example implementations, unreferenced memory addresses in a segment of a storage volume may be identified. Access to the segment of the storage volume may be controlled by one of a plurality of storage volume controllers (SVCs). The plurality of SVCs may control access to respective segments of the storage volume. Indicators of the identified unreferenced memory addresses may be stored in a volatile memory in the one of the plurality of SVCs. In response to an input/output (I/O) command from a host, data may be written to one of the identified unreferenced memory addresses corresponding to one of the indicators stored in the volatile memory. After the data has been written, the one of the indicators may be deleted from the volatile memory. The one of the identified unreferenced memory addresses may not have been made available to other SVCs after being identified.

Abstract: A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.