Abstract: The present disclosure relates to retrieving and executing a Basic Input Output System (BIOS) image that is divided into at least two parts and, more particularly, to retrieving and executing a BIOS image in a blade server environment utilizing a service processor and a blade management agent.

Abstract: Various embodiments of a utility for configuring data sources in a networked computer system are disclosed. A networked computer system may include a number of backend systems hosting a variety of types of data resources including databases produced by a variety of vendors. Application servers running transactional applications as well as many other types of computer systems may be included in the networked system. The data source configuration utility may determine the data source configuration parameters associated with each of the various types of data resources included in the system. When a data source is selected for configuration, the utility may present the configuration parameters corresponding to that particular data source to the user. The utility may create one or more data source configuration files based on parameter values received from the user.

Abstract: One or more programmable clock management components of an apparatus in one example are coupled with a backplane. The one or more programmable clock management components comprise a reconfigurable clock management component. Upon receipt of one or more control signals, the reconfigurable clock management component undergoes a reconfiguration to be able to process one or more frequency signals.

Abstract: An input/output subsystem is configured as a plurality of input/output subsystem images, each of which appears to a program as an independent input/output subsystem. One or more input/output subsystem images of the plurality of input/output subsystem images are managed. An aspect of this management includes managing an input/output (I/O) configuration of an input/output subsystem image. This management may be performed dynamically.

Abstract: A circuit and method for the input of a start signal, a controller being transferred from a first state into a second state as a function of the start signal, the energy consumption of the controller in the second state being greater than in the first state, the circuit having a clocked energy source which emits a timed energy signal, and the start signal is formed as a function of the energy signal.

Abstract: A data transfer unit (13) is provided for use in a clock swapping system which controls data transfer with a data transmission permit signal (rwo) and data reception permit signal (rro). The data transfer unit (13) includes a data latch (21) which latches transfer data in time with a transmission enable signal (ewi) and from which the data is read in time with a reception enable signal (eri), a first FR-FF circuit (31) which delays the transmission enable signal (ewi) for at least one period of a transmission clock (ckw), and a third SR-FF circuit 33 which delays the reception enable signal (eri) for a period of a reception clock (ckr). In the data transfer unit (13), a signal latched by the first SR-FF circuit (31) is latched a series of two times in time with the reception clock (ckr) to generate the reception permit signal (rro) and a signal latched by the third SR-FF circuit (33) is latched a series of two times in time with the transmission clock (ckw) to generate the transmission permit signal (rwo).

Abstract: The power noise removing circuit includes a decoupling capacitor group, a repair circuit unit, a monitoring pad, and a testing unit. The decoupling capacitor group includes a plurality of decoupling capacitors that store noise flowing into an internal power line. The decoupling capacitors are DRAM cell type capacitors. The repair circuit unit controls a connection of each of the decoupling capacitors in the decoupling capacitor group to an external input power line. The monitoring pad measures the amount of current leaking from the decoupling capacitor group. The testing unit controls a connection of the decoupling capacitor group to the monitoring pad. If the decoupling capacitor group is tested as being defective, the defective decoupling capacitor group is made inoperative by disconnection from the external input power line.

Abstract: A method and apparatus may be provided to allow for the enablement or disablement of a computer remotely for servicing or other reasons. The computer may be enabled remotely by one or more circuits that may simulate a system switch turn on or turn off event.

Abstract: A mechanism is provided for configuring a set of devices for a given machine attached to a storage area network. The initial program load firmware and network adapter firmware for each machine on the storage area network are modified to query a storage area network appliance for lists of devices. The storage area network appliance may be identified by a world wide name and may store lists of boot devices, root volume group devices, primary devices, and secondary devices for each machine on the storage area network. The storage area network appliance then listens for queries and returns the appropriate list of devices based on query type and/or boot type. The boot type for a machine may be set to normal boot, maintenance boot, or install boot.

Abstract: Clock speed of the processor in a hard disk drive is controlled during run time to optimize the trade-off between minimizing power consumption and maximizing performance. Processor clock speed is increased during processing of code more performance critical to the disk drive system, while processor clock speed is reduced when less performance critical code is processed. An example of more critical code where processor clock speed is increased is the code executed by the processor from the start of a servo interrupt until output of resulting servo current command is provided from the processor to the actuator controller. To enable changing processor clock speed, an ASIC containing the disk drive processor is selected which provides the ability to switch clock rates of the processor during processor run time.

Abstract: A feeding technique for a storage unit is provided, in which power can be supplied from an optimum power source depending on an operation mode of a cache memory, the stable switching of feeding paths can be performed, and the feeding with high voltage accuracy and small voltage variation can be achieved. For its achievement, the feeding system in the RAID system including a hard disk drive, a disk adaptor, a channel adaptor, and a cache memory is provided. The feeding system includes a DC-DC power source to supply, to the cache memory, the voltage for a normal operation mode in which the data is written/read to/from the cache memory, and a DC-DC power source to supply, to the cache memory, the voltage for a backup operation mode in which the data stored in the cache memory is retained, and the power sources are switched during the feeding depending on the operation mode of the cache memory.

Abstract: A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller. A power-saving control unit controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.