Patents Examined by Harry Vartanian
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Patent number: 6944248Abstract: A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.Type: GrantFiled: May 17, 2001Date of Patent: September 13, 2005Assignee: Bluebrook Associates LLCInventor: Terence Sean Sullivan
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Patent number: 6937666Abstract: A microwave radio assembly is described including a directional antenna wherein the installation and aiming is simplified. The assembly is attached to the wall-mount fix via gimbals mechanism with one rotation axis for azimuth and one for elevation and the assembly preferably includes a sight mechanism including a pair of visual apertures is located in the radio assembly in a line parallel to the radio antenna radiation direction. The radio assembly further includes a modulation cancellation scheme in full duplex mode.Type: GrantFiled: April 24, 2003Date of Patent: August 30, 2005Assignee: Bridgewave Communications, Inc.Inventors: Eliezer Pasternak, Gregg Levin, Idan Bar-Sade, John Park
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Patent number: 6934321Abstract: In a W-CDMA transmission rate estimation method, a maximum likelihood transport format combination is selected from a plurality of transport format combinations representing bit length combinations constituting a plurality of transport channels, each having a variable bit length, on the basis of correlation strengths between a normal encoded bit string and bit strings of data obtained by performing Viterbi decoding processing for data, of a reception output constituted by the respective transport channels, which corresponds to an arbitrary transport channel. A data transmission rate is then estimated on the basis of the selected combination. A W-CDMA transmission rate estimation device is also disclosed.Type: GrantFiled: April 25, 2001Date of Patent: August 23, 2005Assignee: NEC CorporationInventor: Takeshi Sato
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Patent number: 6934325Abstract: A system for executing real-time tasks, such as a multi-line modem, on a client-server network includes a control unit and multiple processing units. The control unit is implementable by the server and each processing unit is implementable by a client or by the server. For the modem, the processing units can either modulate outgoing data and demodulate incoming samples per line or can implement one stage of the modem. For the former embodiment, the control unit assigns one processing unit to each active communication between one modem application on the network and one phone line. For the latter embodiment, the control unit moves the data and samples from one stage to the next.Type: GrantFiled: March 1, 2001Date of Patent: August 23, 2005Assignee: Smart Link Ltd.Inventor: Benjamin Maytal
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Patent number: 6934347Abstract: Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.Type: GrantFiled: December 15, 2000Date of Patent: August 23, 2005Assignee: AlcatelInventors: Santo Maggio, Paolo Taina, Massimiliano Rutar
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Patent number: 6931053Abstract: A peak power regulator is disclosed that functions within a Code Division Multiple Access (CDMA) transmitter to reduce peak power spikes within baseband signals, controlling the out-of-band emissions, and maintaining the in-band signal quality within an acceptable degradation. In-phase and quadrature baseband signals are input to an envelope magnitude predictor within the peak power regulator. The envelope magnitude predictor outputs an estimate for the magnitude of the envelope that will be generated when the inputted baseband signals are modulated. This estimate is input to a multiplier that generates a ration by dividing the estimate by a maximum acceptable envelope magnitude. The ratio is subsequently input to a mapping table that outputs a scaling factor sufficient for reducing peak power spikes. The scaling factor is subsequently subtracted from a value of one and multiplied by first delayed versions of the in-phase and quadrature baseband input signals.Type: GrantFiled: December 5, 2000Date of Patent: August 16, 2005Assignee: Nortel Networks LimitedInventor: Neil N. McGowan
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Patent number: 6931084Abstract: A method of performing an echo phase offset correction in a multi-carrier demodulation system involves the step of differential phase decoding phase shifts based on a phase difference between simultaneous carriers having different frequencies. An echo phase offset is determined for each decoded phase shift by eliminating phase shift uncertainties related to the transmitted information from the decoded phase shift. The echo phase offsets are averaged in order to generate an averaged offset. Finally, each decoded phase shift is corrected based on the averaged offset.Type: GrantFiled: April 14, 1998Date of Patent: August 16, 2005Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Ernst Eberlein, Sabah Badri, Stefan Lipp, Stephan Buchholz, Albert Heuberger, Heinz Gerhaeuser, Robert Fischer
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Patent number: 6925136Abstract: A frequency and phase synchronizer system comprises a processor for executing a sequence of operations, which include: a) initializing a frequency error estimate value and phase error estimate value; b) separating discrete samples of a continuous phase modulation signal into a first sequence of odd numbered samples of the signal, and a second sequence of even numbered samples of the signal; c) determining an unknown frequency offset value from the first and second sequences, frequency error estimate, and phase error estimate; d) determining an unknown phase offset value from the first and second sequences, frequency error estimate, phase error estimate, and a first discrete data sample of said discrete samples of the continuous phase modulation signal; f) updating the frequency error estimate from the unknown frequency offset value; and updating the phase error estimate from the unknown phase offset value.Type: GrantFiled: August 29, 2001Date of Patent: August 2, 2005Assignee: The United States of America as represented by the Secretary of the NavyInventor: Ray H. Pettit
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Patent number: 6922454Abstract: A radio receiving system, which receives an input signal in a direct conversion receiving mode through the use of a plurality of cascaded channel filters, each including a complex coefficient filter, to obtain a desired waveform, wherein a center frequency of a preliminary channel filter corresponds more closely with the frequency of the desired waveform than a center frequency of a subsequent channel filter.Type: GrantFiled: October 23, 2002Date of Patent: July 26, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Gen-ichiro Ohta, Kazunori Inogai, Hiroaki Sudo, Fujio Sasaki
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Patent number: 6922445Abstract: A method and system for selective mode adaptation for transmitting data by spatial multiplexing applicable in communications systems with a transmit unit having multiple transmit antennas or multiple transmit units and a receive unit having multiple receive antennas. A channel descriptor, such as channel matrix H or a channel matrix filter , with has sub-descriptors corresponding to the transmit antennas is determined and a quality parameter, such as signal-to-interference and noise ratio, signal-to-noise ratio or power level are chosen. The quality parameter is assigned a threshold and the sub-descriptor or sub-descriptors whose quality parameters do not meet the threshold are identified and deactivated.Type: GrantFiled: June 30, 2000Date of Patent: July 26, 2005Assignee: Intel CorporationInventors: Hemanth Sampath, Peroor K. Sebastian, Arogyaswami J. Paulraj
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Patent number: 6917654Abstract: A communication system is disclosed that encodes multiple bits of digital data on a single analog signal cycle. The communication system includes a digital data encoding system that receives the multiple bits of digital data and looks up the digital data in a Digital-to-Analog (D/A) conversion table. The D/A conversion table correlates the multiple bits of digital data to amplitudes of an analog signal and yields amplitudes values. The digital data encoding system then generates the analog signal cycle based on the amplitude values. The digital data encoding system advantageously increases the bandwidth available to customers, which is particularly important to help solve “last mile” bandwidth problems. The communication system also includes a digital data decoding system on the receiver side that decodes the multiple bits of digital data from the analog signal cycle using an Analog-to-Digital (A/D) conversion table.Type: GrantFiled: April 23, 2001Date of Patent: July 12, 2005Assignee: Sprint Communications Company L.P.Inventor: Salvador Cerda, Jr.
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Patent number: 6912258Abstract: A single integrated circuit multi-standard demodulator includes an adaptive inverse channel estimator for frequency domain equalization which employs a recursive least square cost function in estimating the inverse channel from the received signal and an error estimate. Utilizing a diagonal correlation matrix, the solution to may be determined utilizing fewer computational resources than required by conventional frequency domain equalizers, shifting from a computational intensive to memory intensive implementation. The memory requirement is fully satisfied by memory available within conventional OFDM decoders, and the necessary computational resources may be readily mapped to the resources available within such decoders, improving integrated circuit cost-effectiveness of the multi-standard demodulator.Type: GrantFiled: April 23, 2001Date of Patent: June 28, 2005Assignee: Koninklijke Philips Electtronics N.V.Inventor: Dagnachew Birru
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Patent number: 6912242Abstract: A low power RF receiver (1) has an antenna (2), a reception and shaping stage (3) for the radio-frequency signals provided by the antenna, a 12-channel correlation stage (7) receiving intermediate signals (IF) shaped by the reception stage (3), and a microprocessor (12) connected to the correlation stage for calculating X, Y and Z position, velocity and time data as a function of data provided by the radio-frequency signals, such as GPS signals, transmitted by satellites. Each channel includes a correlator (8) associated with a controller (9), which also includes a digital signal processing algorithm to allow all the synchronisation tasks for acquiring and tracking a satellite to be performed autonomously when the channel (7?) is set in operation, and to lock onto the satellite. Buffer registers (11) are placed at the interface between the correlation stage (7) and the microprocessor (12) for the mutual transfer of data.Type: GrantFiled: June 22, 2001Date of Patent: June 28, 2005Assignee: Asulab S.A.Inventors: Pierre-André Farine, Jean-Daniel Etienne, Ruud Riem-Vis, Elham Firouzi
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Patent number: 6909761Abstract: A time division multiple access communication system is provided having multiple sub-channels according to known quadrature amplitude modulation techniques. Each sub-channel has a pre-determined time duration and is divided by a pre-determined number of symbol position time divisions. The symbol positions carry color codes and ACP codes in addition to sync, pilot and data symbols. Pilot symbols in the second half of the slot are replaced with dual purpose color code and ACP symbols. The dual purpose symbols are either modulated with a lower order modulation than data symbols or are repeated values of dedicated symbols located earlier in the same slot, or both. Slot throughput is attained with a minimal bit error rate penalty.Type: GrantFiled: December 19, 2002Date of Patent: June 21, 2005Assignee: Motorola, Inc.Inventors: Michael N. Kloos, Michael S. Palac, Yashpal Thind
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Patent number: 6907083Abstract: An apparatus for frequency content separating an input signal is disclosed. The apparatus comprises a plurality of frequency splitting stages, each stage including one or more up-converter and down-converter pairs. An up-converter and down-converter pair serves (i) to receive a complex input signal representing an input bandwidth and (ii) to output a first complex output signal representing an upper portion of the input bandwidth and a second complex output signal representing a lower portion of the input bandwidth. The upper portion and the lower portion being contiguous and together representing the input bandwidth portion.Type: GrantFiled: February 1, 2001Date of Patent: June 14, 2005Assignee: R F Engines LimitedInventor: John Lillington
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Patent number: 6901111Abstract: An interface circuit (100) and method for interfacing received digital signals, relative to a first ground potential, for transmission on the bus, relative to a second ground potential. A transformer (106) passes edges of the received digital signals. A Schmitt trigger (110) reconstructs signals from the edges of signals passed by the transformer, so as to produce digital signals, for transmission on the bus, relative to the second ground potential. The Schmitt trigger bias points may be set by an oscillators incorporating another Schmitt triggers (120) located on the same semiconductor die to reduce temperature variability.Type: GrantFiled: January 12, 2001Date of Patent: May 31, 2005Assignee: Motorola, Inc.Inventors: Peter Miller, Peter Hartnett
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Patent number: 6898254Abstract: A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a signal-to-noise ratio based on the mean and variance of soft-output estimates. The decoding process is aborted based on a comparison of the generated signal-to-noise ratio to a predetermined threshold.Type: GrantFiled: January 29, 2001Date of Patent: May 24, 2005Assignee: Texas Instruments IncorporatedInventors: Tod D. Wolf, William J. Ebel, Sr.
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Patent number: 6891901Abstract: An output signal to be transmitted via an especially two wire transmission line (A, B), which is composed of a transmission signal and a DC supply voltage, is generated by a data transmission device especially designed in the form of a SLIC circuit. Using a control circuit (5-8), which tracks the DC supply voltage on the output side of the transmission device (1-3) in such a manner that the level of the DC supply voltage does not decrease, it is possible to ensure that both the specified requirements concerning the maximally admissible DC voltage drop as well as the specified requirements concerning the reflection attenuation are met.Type: GrantFiled: January 3, 2001Date of Patent: May 10, 2005Assignee: Infineon Technologies, AGInventor: Bernd Heise
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Patent number: 6885700Abstract: A charge-based frequency measurement BIST (CF-BIST) for clock circuits and oscillator circuits is described that requires no outside test stimulus and produces a digital test output. The CF-BIST technique performs structural and defect-oriented testing and uses existing blocks to save die area. The technique adds a multiplexer to the non-sensitive digital path. The system uses the existing VCO as the measuring device and divide-by-N as a frequency counter to reduce the area overhead. The described technique produces an efficient pass/fail evaluation, low-cost and practical implementation of on-chip BIST structure.Type: GrantFiled: September 25, 2000Date of Patent: April 26, 2005Assignee: University of WashingtonInventors: Seongwon Kim, Mani Soma
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Patent number: 6882684Abstract: An automatic gain control circuit includes a first portion which calculates a first error amount, and a second portion which calculates a second error amount. Both calculated error amount is sent to a determination module. Further, an integrator integrates an error amount, a difference between a power of an input signal and an average power of an eye pattern for example. The determination determines whether the integrated error amount exceeds a predetermined value or not, and output either of the first error amount and the second error amount based on the determination.Type: GrantFiled: January 10, 2001Date of Patent: April 19, 2005Assignee: Fujitsu LimitedInventors: Takashi Kaku, Hideo Miyazawa
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Patent number: 4944917Abstract: Disclosed is a method for inhibiting corrosion of metal surfaces in contact with H.sub.2 S-containing acid gases streams and aqueous amine scrubbing solutions, which method comprises: contacting the H.sub.2 S-containing stream with amine scrubbing solution in the presence of an effective amount of an ammonium or alkali-metal thiosulfate salt and an effective amount of sulfide and/or hydrosulfide ions.Type: GrantFiled: December 28, 1987Date of Patent: July 31, 1990Assignee: Exxon Research and Engineering CompanyInventors: Patrick C. Madden, II, Z. Andrew Foroulis