Abstract: A memory unit for a aircraft flight data recorder system uses an electronically erasable solid state memory for storing the flight data and a memory controller circuit are housed in a penetration resistant, thermally insulated enclosure. Power dissipation within the insulated enclosure is minimized by an external switching circuit that applies operating potential to the solid state memory only when data are being transferred to and from the memory circuit. A data protection circuit, located within the insulated enclosure inhibits memory write and erase operations whenever the system operating potential falls below a predetermined level. In continuously storing flight data, the oldest stored data is overwritten with newly arriving flight data and the memory controller maintains an erased boundary that defines the beginning and end of the recorded data. A power monitor circuit, located outside the insulated enclosure, resets the memory controller to the erased boundary following a power interruption.

Abstract: A text comparator receives data stored in a mass storage device. The text comparator includes word logic, delimiter logic, set logic, set combination logic, proximity logic, and programming logic. The delimiter logic serves to monitor the characters transferred from the mass storage device and provides discrete signals depicting whether the character being transferred is a predefined delimiter character. The word logic serves to store data regarding predefined words (i.e., strings of characters) which are to be located and provides output word signals indicating when such predefined words have been located. The set logic receives the delimiter signals and word signals and provides output signals when selected words are located in the same sentence, same paragraph, etc., as desired. The set combination logic serves to combine the signals from the set logic in order to generate output signals in response to more complex search strategies than can be easily detected by the set logic.

Abstract: A programmable electronic calculator is provided for numerical evaluation of mathematical problems through application of one or more mathematical operators to each input numerical operand of a mathematical problem according to accepted rules of mathematical combinations. Entry of each numerical operand and mathematical operator is accompanied by a printed record of that numerical operand and that mathematical operator so that the mathematical problem may be continually monitored as it is being entered. Depression of an equals key is followed by evaluation of previously designated operations and printing of the result. One may select a learn mode in which steps are entered in a learn memory by working out a mathematical problem, each selected operation corresponding to a step in the learn memory.

Abstract: A data transfer system for transferring data from magnetic tape peripheral units to a peripheral-controller for temporary storage and subsequent transfer to a host computer. A tape control unit, connected to the magnetic tape peripheral units, provides clock signals to a synchronization logic circuit which controls the transfer of data through two sequential latching registers to a buffer memory in the peripheral-controller. The two sequential latching registers function as a buffering delay element together with an automatic read logic unit which allows the read logic unit to use a lesser number of cycle-steal times than would ordinarily be required, while still controlling a steady uninterrupted flow of data words.

Abstract: Variable length data (e.g., for hospital patients) is embedded in a B-tree type index structure of a relational data base. A logically related inverted B-tree index is used to access the original index. Access time, and storage space for the inverted lists, are decreased by data compression techniques and by encoding certain inverted list parameters in sparse array bit maps.

Abstract: A code track on a rotable member (e.g., a disc) defines a pseudo-random sequence of binary digits consisting of ones and noughts. The pseudo-random sequence extends continuously around the rotatable member and includes a given number of n consecutive noughts. The binary digits of the sequence are arranged so that each group of n adjacent digits is different from each other group of n adjacent in the pseudo-random sequence. A reading mechanism is operatively positioned relative to the code track for reading n consecutive digits of the pseudo-random sequence, wherein each n consecutive digits of the pseudo-random sequence define a position of the rotatable member.

Abstract: A peripheral-controller (designated as a data-link-processor) manages data transfers between a main host computer and a magnetic tape peripheral unit. The peripheral-controller uses a common front end providing an instruction sequencing unit and a buffer memory to store data-in-transit in six blocks of 256 words each. A peripheral-dependent circuit unit of the peripheral-controller can provide automatic read or automatic write data transfers between the buffer memory and the magnetic tape peripheral unit without further attention from said instruction sequencing unit.

Abstract: In a data processing system for use in accessing a main memory from each of a central processing unit and a channel unit through a common data bus, an address translation circuit is incorporated in the central processing unit so as to translate each logical address into a real address physically allotted to the main memory and is used in common by the central processing unit and the channel unit. Address translation is carried out by the address translation circuit selectively for the central processing unit and the channel unit. When the main memory is accessed from the channel unit through the central processing unit, an indication signal is delivered from the main memory only to the central processing unit to indicate either reception or supply of a data group. The central processing unit energizes the channel unit to assign the data bus to the channel unit. Thereafter, the data group is transferred between the main memory and the channel unit through the data bus.

Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: A memory system has a first memory such as a magnetic bubble memory and a second memory such as a RAM having a faster access time than the first memory. The first memory is divided into a plurality of blocks each of which has program steps stored therein. The second memory has a plurality of unit chains which correspond to the blocks of the first memory respectively and in each of which step information representative of the number of steps stored in the corresponding block and pointer information indicative of a connection to a next block are stored. The step information in the unit chains are successively read in accordance with predetermined start block information and the pointer information to count the total number of steps on the basis of the read step information. From the first memory is read information in the block corresponding to the unit chain of the second memory with respect to which the counting is made when the counted number of steps reaches or exceeds a program step number to be detected.

Abstract: Apparatus controls sequential direct memory access (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer memory has an overrun area associated with it. Prior to transfers from the buffer memories to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer memory with data from the next buffer memory. During the DMA transfer, when the first buffer memory becomes empty a request is made to a computer to restart the DMA operation on the next sequential buffer, but while the request is being serviced, data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffer memories, after the first buffer memory is full, an interrupt is generated and incoming data is stored in the first buffer memory's overrun area while the interrupt is being serviced.

Abstract: A request buffer apparatus controls a plurality of access requests to devices to be accessed (e.g., memory banks) commonly used by a plurality of accessing devices (e.g., a CPU, channels, and DMA units) in a data processing system. The apparatus has a request buffer means which has a plurality of buffers for storing the access requests. Write/read operations of the requests in and from the request buffer means are randomly performed in accordance with the status of the device to be accessed corresponding to the request stored in the buffer. Requests corresponding to the same device to be accessed are written in the empty buffers of the request buffer means in the order they are generated, and are read out from the request buffer means in the order that they are written. Each device to be accessed has a buffer write address generating means, and the buffer write status of each buffer is indicated so as to obtain the next buffer write address.

Abstract: In a sort circuit comprised of m sort stages, the sort stages perform respective sorts, in parallel, on each input word as it is received. In particular, in the j.sup.th one of the stages, j=1,2, . . . m, a bit is associated with each different possible pattern of the values of the D.sub.j highest-order digits in the input word, D.sub.1 >D.sub.2 > . . . D.sub.m. As each input word is received, the values of its D.sub.j higher-order digits are examined and the associated bit is set.During output processing, the j.sup.th stage of the sort circuit receives from the (j+1).sup.st stage a D.sub.j+1 -digit pattern representing the D.sub.j+1 highest-order digits of a word or words previously input to the sort circuit. The D.sub.j+1 -digit pattern is used to identify the bits within the j.sup.th stage associated with the D.sub.j -digit patterns whose D.sub.j+1 highest-order digits match the input pattern. The bits thus identified are processed within the j.sup.

Abstract: In an apparatus as a working aid for blind and partially sighted people for communication with a computer system with a keyboard and with a screen output for a screen as an output device for determining a raster coordinate point of said screen output and for producing an electrical data signal corresponding to said coordinate point for the repeat and reliable finding of a particular information corresponding to a certain coordinate point, at least two data call-up devices are provided capable of calling up the data corresponding to a certain coordinate point in the form of only end position-stable sliders movable independently of one another in two coordinate directions perpendicular to one another.

Abstract: An interface circuit in a television receiver selects two pulses from a pulse train for transfer to a digital computer. The interface circuit includes first and second logic elements, a counter and a comparator for enabling a gating circuit to transfer the selected two pulses to the digital computer.

Abstract: A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode logic block for generating a DATA TRANSMIT ENABLE SIGNAL to permit the bipolar buffer to transmit data signals from the peripheral device to a system bus. The circuit also provides for a second slave mode logic block and a master mode logic block for generating a DATA RECEIVE ENABLE block to permit the bipolar buffer to transmit data signals from the system bus to the peripheral device. Each slave mode logic block is responsive to condiion signals, such as CHIP SELECT and READ/WRITE. Each master mode logic block is responsive to timing signals and signals generated internally within the periphel device so that the master mode DATA RECEIVE and DATA TRANSMIT signals occur only in predetermined timing cycles.

Abstract: The invention provides apparatus and method to verify appropriate program execution. Hardware external to a processor includes a resettable timer and a shift register for storing and shifting a bit pattern. Internally of the processor a bit pattern is also manipulated by a routine which also outputs a clock signal. A selected bit from each of the patterns is compared on each clock signal. If the clock signal repeats at a sufficiently rapid rate to keep the timer from expiring and, if the comparison is favorable, the processor is allowed to run; otherwise it is reset.

Abstract: The invention disclosed provides circuitry which is selectively operable either as an input point or as an output point in a programmable controller having multiple input and output points for exchanging signals between a central processing unit (CPU) of the controller and a process being controlled. Preferably, operation as an input point or as an output point is under control of the CPU. The invention includes a common input/output terminal for terminating both input and output devices; an input return terminal for terminating a return conductor from the input device; an output return terminal for terminating a return conductor from the output device; a preload resistor connected between the input/output terminal and the output return terminal so that a status signal is developed across the preload resistor indicating the status (generally, open or closed) of the input device; and an insulated gate transistor (IGT) connected between the input/output terminal and the input return terminal.

Abstract: A vending machine stores a plurality of video game programs which may be selected for purchase. The game program is transferred to a programmable cartridge which the user inserts into the machine. The programmable cartridge is then removed for use on a separate video game unit. The programmable cartridge includes a use interval circuit which is preset by the vending machine to expire after a time interval. When expired, the transferred program is rendered inoperable.

Abstract: .[.An electronic franking machine, for example a postal franking machine, has a digital electronic input register, for storing a selected franking value fed in for use in the next franking operation of the machine, and a digital electronic total register which accumulates an indication of the total of the respective franking values used for such operations of the machine since this register was last reset. The machine also has an electrically adjustable printing device, for printing the selected franking value in each franking operation. The printing device is housed in a relatively massive stationary unit of the machine, and the electronic registers and associated circuitry are housed in a relatively light portable unit that is readily separable from the stationary unit to facilitate resetting by a remote authority..]..Iadd.