Abstract: Systems, methods, and devices for managing media storage and delivery, including obtaining, by a media access function (MAF), a Graphics Language Transmission Format (glTF) file corresponding to a scene; obtaining from the glTF file a uniform resource locator (URL) parameter indicating a binary data blob; determining that the binary data blob has a Concise Binary Object Representation (CBOR) format; converting the binary data blob into an object having a JavaScript Object Notation (JSON) format using a CBOR parser function implemented by the MAF; and obtaining media content corresponding to the scene based on the object.

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

Abstract: A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double precision operations, the GPU stores the corresponding operands at the operand registers. Over a plurality of execution cycles, the GPU sequences transfer of operands from the set of operand registers to a designated double precision operand register. During each execution cycle, the double-precision ALU executes a double precision operation using the operand stored at the double precision operand register.

Abstract: A display method and a display apparatus are provided in the present disclosure. The display method, applied to a display apparatus, includes obtaining a first image signal from an electronic apparatus, where the first image signal is a signal configured for displaying on one display apparatus; according to the first image signal, outputting first image data in a first display region; obtaining first instruction, where the first instruction is configured to instruct that the first display region is at least divided into a first display sub-region and a second display sub-region; obtaining a second image signal from the electronic apparatus, where the second image signal is a signal configured for displaying on at least two display apparatuses; and according to the second image signal, outputting first sub-image data in the first display sub-region and outputting second sub-image data in the second display sub-region.

Abstract: A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to obtain a bounding box for a compressed box data item of the compressed box node.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for GPR optimization in a GPU based on a GPR release mechanism. More specifically, a GPU may determine at least one unutilized branch within an executable shader based on constants defined for the executable shader. Based on the at least one unutilized branch, the GPU may further determine a number of GPRs that can be deallocated from previously allocated GPRs. The GPU may deallocate, for a subsequent thread within a draw call, the number of GPRs from the previously allocated GPRs during execution of the executable shader based on the determined number of GPRs to be deallocated.

Abstract: Systems, devices, and methods for generating, processing, assembling, and/or formatting data for display are described. Example display controllers are described in which image data is stored in a framebuffer, and a compositor selectively retrieves portions of the image data. At least one P-operator produces lines of intermediate P-operated data by performing at least one intra-line operation on the image data retrieved by the compositor, such as repeating or reordering pixels of the image data. A Q-operator produces a stream of pixel data by performing inter-line operations on the intermediate P-operated data, such as interpolating between lines of the P-operated data. A display is driven according to the stream of pixel data.

Abstract: Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray.

Abstract: A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be “recycled” for use by the pipeline.

Abstract: Apparatuses, systems, and techniques to generate blue noise masks for real-time image rendering and enhancement. In at least one embodiment, a vector-valued noise mask is generated and applied to one or more images to generate one or more enhanced images for image processing (e.g., real-time image rendering). In at least one embodiment, the noise mask includes vector values per pixel and is able to handle the temporal domain (e.g., add time to the spatial domain) to improve image quality when rendering images over multiple frames.

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing non-RAM memory to implement large digital display emulations. An embodiment operates by generating, by an emulator device, a pixel map of a digital display, wherein the pixel map comprises a plurality of pixels representative of a plurality of light emitting elements arranged on a viewable surface of the large digital display. A distance and orientation of a virtual viewer to the viewable surface of the large digital display is generated and the emulator device emulates the large digital display based on the pixel map and the distance and the orientation of the virtual viewer and renders the digital content based on the emulated large digital display.

Abstract: This invention provides an apparatus having an acquisition unit for acquiring data representing a measured value concerning a cultivation situation in a farm field, and a display control unit for displaying the measured value, wherein if the result of aggregating the measured value represented by the data for each attribute value of a first attribute is displayed and a user selects a first attribute value of the first attribute, the display control unit aggregates the measured value having the first attribute value, for each attribute value of a second attribute, and displays the measured value, and if the user selects a second attribute value of the second attribute, the display control unit aggregates the measured value having the second attribute value of the second attribute, for each attribute value of the first attribute, and displays the measured value.

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

Abstract: A graphics pipeline cache reconstruction operation is implemented to reconstruct one or more graphics pipeline caches for a current client gaming session based on one or more pipeline structures. The pipeline structures each represent a graphical object rendered during a respective previous client gaming session and are used to reconstruct one or more graphics pipeline caches that include graphics pipeline cache objects related to the graphical objects of the pipeline structures. These graphics pipeline cache objects are used to initialize one or more graphics pipelines used to render the graphical objects in a gaming application for a current client gaming session.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

Abstract: The present invention provides a motion content based dynamic frame rate conversion method for displaying a video by a display device, comprising: detecting motion content of the video and generating a control signal for controlling a display color depth based on the motion detection result. The video is displayed with a lower color depth at a higher frame rate than a standard configuration of the display device if the motion detection result indicates that the video contains appreciable amount of motion content; and the video is displayed with a higher color depth at a lower frame rate than the standard configuration of the display device if the motion detection result indicates that the video is relatively static. The present invention can facilitate the display device to dynamically convert its display output formats according to motion content of the video to further optimize the display quality.

Abstract: A display system receives first timing information prior to the display system entering a panel self-refresh (PSR) mode. The display system supports a range of refresh rates. Prior to the display system entering the PSR mode, first timing information indicating a first refresh rate that is lower than a maximum refresh rate supported by the display system is received by the display system. The display system then refreshes images at a second refresh rate that is less than or equal to the first refresh rate using a frame stored in a buffer prior to entering the PSR mode. In some cases, the processing unit also receives second timing information from the display system in response to initiating an exit from a panel self-refresh (PSR) mode. The second timing information indicates a current scanout line that is used to schedule transmission of a subsequent frame.

Abstract: An electronic device may include a first display pipeline that may output image data via an output path. The electronic device may include first frame merge circuitry coupled to the output path. The electronic device may also include a first multiplexer coupled to the first frame merge circuitry and to the output path. The first multiplexer may transmit the image data from the output path to an electronic display, and, in response to a first control signal associated with the first frame merge circuitry generating a merged output, the first multiplexer transmits the merged output to the electronic display.