Patents Examined by Hau Nguyen
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Patent number: 9466102Abstract: A system for performing image reconstruction in a multi-threaded computing environment includes one or more central processing units executing a plurality of k-space components and a plurality of graphic processing units executing a reconstruction component. The k-space components executing on the central processing units include a k-space sample data component operating in a first thread and configured to receive k-space sample data from a first file interface; a k-space sample coordinate data component operating in a second thread and configured to receive k-space sample coordinate data from a second file interface; and a k-space sample weight data component operating in a third thread and configured to retrieve k-space sample weight data from a third file interface.Type: GrantFiled: September 19, 2013Date of Patent: October 11, 2016Assignee: SIEMENS CORPORATIONInventors: Mariappan S. Nadar, Steven Martin, Alban Lefebvre, Jun Liu
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Patent number: 9466089Abstract: A signal processor of the invention includes a host processor, a command queue, a graphics decoding circuit, a video decoding circuit, a composition engine and two display buffers. The host processor generates graphics commands and sets a video flag to active based on graphics encoded data, video encoded data and mask encoded data from a network. The command queue asserts a control signal according to the graphics commands. The graphics decoding circuit generates the graphics frame and two surface mask while the video decoding circuit generates the video frame and a video mask. The composition engine transfers the graphics frame, the video frame or a content of one of two display buffers to the other display buffer according to the video mask and the two surface masks when the control signal is asserted or when the video flag is active.Type: GrantFiled: October 7, 2014Date of Patent: October 11, 2016Assignee: ASPEED TECHNOLOGY INC.Inventor: Chung-Yen Lu
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Patent number: 9448840Abstract: A runtime management system is described herein that allows a hosting layer to dynamically control an underlying runtime to selectively turn on and off various subsystems of the runtime to save power and extend battery life of devices on which the system operates. The hosting layer has information about usage of the runtime that is not available within the runtime, and can do a more effective job of disabling parts of the runtime that will not be needed without negatively affecting application performance or device responsiveness. The runtime management system includes a protocol of communication between arbitrary hosts and underlying platforms to expose a set of options to allow the host to selectively turn parts of a runtime on and off depending on varying environmental pressures. Thus, the runtime management system provides more effective use of potentially scarce power resources available on mobile platforms.Type: GrantFiled: December 29, 2014Date of Patent: September 20, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Akhilesh Kaza, Gunjan A. Shah, Shawn T. Oster, Jonathan D. Sheller, Alan C. T. Liu, Nimesh I. Amin, Randal J. Ramig
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Patent number: 9448760Abstract: Remote desktop servers include a display encoder that maintains a secondary framebuffer that contains display data to be encoded and transmitted to a remote client display and a list of display primitives effectuating updated display data in the secondary framebuffer. The display encoder submits requests to receive the list of drawing primitives to a video adapter driver that receives and tracks drawing primitives that, when executed, update a primary framebuffer.Type: GrantFiled: December 2, 2014Date of Patent: September 20, 2016Assignee: VMware, Inc.Inventors: Dustin Byford, Anthony Cannon, Ramesh Dharan
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Patent number: 9436451Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.Type: GrantFiled: November 13, 2015Date of Patent: September 6, 2016Assignee: GOOGLE INC.Inventors: Gavriel State, Nicolas Capens, Luther Johnson
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Patent number: 9429679Abstract: Systems and methods for structured and unstructured reservoir simulation using parallel processing on GPU clusters to balance the computational load.Type: GrantFiled: February 26, 2015Date of Patent: August 30, 2016Assignee: Landmark Graphics CorporationInventor: John Edwin Killough
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Patent number: 9430202Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.Type: GrantFiled: November 13, 2015Date of Patent: August 30, 2016Assignee: GOOGLE INC.Inventors: Gavriel State, Nicolas Capens, Luther Johnson
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Patent number: 9412317Abstract: An object of the present invention is to provide a display device and a method of driving it, capable of displaying images properly even upon asynchronous input of image data while taking advantages of decreased power consumption implemented by intermission driving. When there is an external input of new image data (image F) in a non-refreshing period in an intermission driving display device which performs intermittent refreshing based on the latest image data that is inputted in and read out from a frame memory, a coercive refreshing is started immediately based on the new image data (image F) (see the sixth frame period). Also, when there is an external input of image data (image G) during a refreshing period for the image F, the ongoing frame period including the refreshing of the image F is completed and immediately thereafter, a coercive refreshing based on the image data (image G) is started (see the ninth frame period).Type: GrantFiled: February 28, 2013Date of Patent: August 9, 2016Assignee: Sharp Kabushiki KaishaInventors: Noriyuki Tanaka, Kouji Kumada
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Patent number: 9405586Abstract: A hub mechanism for use in a multiple graphics processing unit (GPU) system includes a hub routing unit positioned on a bus between a controller unit and multiple GPUs. The hub mechanism is used for routing data and commands over a graphic pipeline between a user interface and one or more display units. The hub mechanism also includes a hub driver for issuing commands for controlling the hub routing unit.Type: GrantFiled: January 13, 2014Date of Patent: August 2, 2016Assignee: Lucidlogix Technologies, Ltd.Inventor: Offir Remez
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Patent number: 9398215Abstract: Systems and methods to generate stereoscopic panoramas obtain images based on captured images. The obtained images may be processed and/or preprocessed, for example to compensate for perspective distortion caused by the non-ideal camera orientation during capturing, to reduce vertical parallax, to align adjacent images, and/or to reduce rotational and/or positional drift between adjacent images. The obtained images may be used for interpolating virtual in-between images on the fly to reduce visible artifacts in the resulting panorama. Obtained and/or interpolated images (or image fragments) may be stitched together to form a stereoscopic panorama.Type: GrantFiled: September 23, 2013Date of Patent: July 19, 2016Assignees: ETH ZURICH, DISNEY ENTERPRISES, INC.Inventors: Christian Richardt, Henning Zimmer, Yael Pritch, Alexander Sorkine Hornung
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Patent number: 9384713Abstract: Typical hybrid graphics systems operate in either a “high-performance mode” or in an “energy saver mode.” While operating in the high-performance mode, a discrete graphics processing unit (dGPU) performs high-performance graphics processing operations and also receives and satisfies access requests targeting a configuration space within the dGPU. While operating in the energy saver mode, an integrated graphics processing unit (iGPU) performs graphics processing operations and the dGPU is powered down. In this scenario, a system management unit (SMU) intercepts and satisfies access requests targeting the dGPU. Since access requests targeting the dGPU are satisfied while the dGPU is powered down, the dGPU continues to be enumerated in the system using the same system resources as originally granted, and can therefore be switched to for implementing high-performance mode more quickly than if it was removed, and required a complete plug-and-play re-enumeration and re-allocation of system resources.Type: GrantFiled: July 27, 2009Date of Patent: July 5, 2016Assignee: NVIDIA CorporationInventors: David Wyatt, Mark A. Overby, Hon Fei Chong
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Patent number: 9384583Abstract: An application executing on a rendering computer invokes a physics function request, e.g., to model the movement and interaction of objects to be rendered. The physics function request specifies a physics function to be performed on input data. Physics function request data is formatted for transmission over a network. The physics computer receives the physics function request data and performs an associated physics function using a physics GPU to generate physics computation result data. The physics computation result data is transmitted to the rendering computer over the network. A rendering GPU renders an image using the physics computation result data.Type: GrantFiled: October 27, 2006Date of Patent: July 5, 2016Assignee: NVIDIA CorporationInventor: Franck Diard
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Patent number: 9377845Abstract: For frame buffer power management, a frame buffer includes a write circuit and a read circuit, and drives a display. A power management module terminates power to the frame buffer in response to a power reduction policy being satisfied.Type: GrantFiled: May 9, 2014Date of Patent: June 28, 2016Assignee: Lenovo (Singapore) PTE. LTD.Inventor: Mark Charles Davis
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Patent number: 9355430Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.Type: GrantFiled: September 20, 2013Date of Patent: May 31, 2016Assignee: NVIDIA CorporationInventors: Eric B. Lum, Cass W. Everitt, Henry Packard Moreton, Yury Y. Uralsky, Cyril Crassin, Jerome F. Duluk, Jr.
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Patent number: 9342901Abstract: A method for generating a shader that is used by a rendering engine to render a visual representation of a computer model. A shader generation engine receives a set of surface data that describes a surface in view of various lighting conditions. The shader generation engine compresses the set of surface data to generate a compressed representation of the set of surface data based on a selected compression algorithm. The shader generation engine generates a shader based on the compressed representation that is configured to be implemented with a rendering engine, and generates a set of shader data based on the compressed representation that includes a set of material characteristics for coloring pixels of the visual representation. Advantageously, the shader generation process is simplified because different compression algorithm-rendering engine shader combinations can be generated without manually programming the shaders.Type: GrantFiled: October 27, 2008Date of Patent: May 17, 2016Assignee: AUTODESK, Inc.Inventors: Jérôme Maillot, Eric Bourque
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Patent number: 9342860Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.Type: GrantFiled: September 11, 2014Date of Patent: May 17, 2016Assignee: Imagination Technologies, LimitedInventor: Jonathan Redshaw
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Patent number: 9336563Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.Type: GrantFiled: January 24, 2014Date of Patent: May 10, 2016Assignee: Apple Inc.Inventors: Joseph P. Bratt, Peter F. Holland, Shing Horng Choo, Timothy J. Millet, Brijesh Tripathi
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Patent number: 9336560Abstract: The disclosed embodiments provide a system that facilitates seamlessly switching between graphics-processing units (GPUs) to drive a display. In one embodiment, the system receives a request to switch from using a first GPU to using a second GPU to drive the display. In response to this request, the system uses a kernel thread which operates in the background to configure the second GPU to prepare the second GPU to drive the display. While the kernel thread is configuring the second GPU, the system continues to drive the display with the first GPU and a user thread continues to execute a window manager which performs operations associated with servicing user requests. When configuration of the second GPU is complete, the system switches the signal source for the display from the first GPU to the second GPU.Type: GrantFiled: August 4, 2014Date of Patent: May 10, 2016Assignee: Apple Inc.Inventors: Thomas W. Costa, Simon M. Douglas, David J. Redman
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Patent number: 9330495Abstract: The present disclosure provides for path rendering including receiving, with a graphics processing unit (GPU), data indicative of a path segment of a path to be rendered. The systems and methods render the path segment by performing a fill of the path segment, which includes tessellating the path segment into a first plurality of primitives including a triangle per primitive, storing a first plurality of primitives in a stencil buffer, and drawing a bounding box of the path segment and rendering the bounding box with a stencil test enabled. The systems and methods also stroke the path segment, including tessellating the path into a second plurality of primitives, re-tessellating the second plurality of primitives, cutting the second plurality of primitives according to a dash pattern, creating a cap at a location of a cut, and creating a triangulation of a stroke and rasterizing the stroke based on the triangulation.Type: GrantFiled: March 15, 2013Date of Patent: May 3, 2016Assignee: QUALCOMM IncorporatedInventors: Vineet Goel, Usame Ceylan
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Patent number: 9324128Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred or entirely avoided as color data values of primitives of an image are stored. An apparatus includes a processor element; and a logic to store color data values of a block of pixels of the image in a first portion of a cache line, store an indication of the first portion as written and of a second portion of the cache line as not in a per-portion table, evict contents of the first and second portions, and store the contents of the first portion in an image data and store a color data value of a clear color in place of the contents of the second portion in the image data in response to the indications stored in the per-portion table. Other embodiments are described and claimed.Type: GrantFiled: March 14, 2013Date of Patent: April 26, 2016Assignee: INTEL CORPORATIONInventors: Steven J. Spangler, Prasoonkumar Surti, Christopher D. Berry, Hiroshi Akiba