Abstract: A thin-film structural body formed by using a semiconductor processing technique and a manufacturing method thereof, and particularly a thin-film structural body constituting a semiconductor acceleration sensor and a manufacturing method thereof. The thin-film structural body allows the thin-film member to be easily stress-controlled, and easily makes the film-thickness of the thin-film member thicker. The thin-film member forms a mass body and, beams and fixed electrodes of the semiconductor acceleration sensor are constituted by a plurality of doped polysilicon thin-films that are laminated by performing a step of film deposition of polysilicon while, for example, phosphorous is being doped as impurities plural times.

Abstract: An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: A method to correct critical dimension errors during a semiconductor manufacturing process. The method includes providing a first semiconductor device. The first semiconductor device is analyzed to determine at least one critical dimension error within the first semiconductor device. A dose of electron beam exposure to correct the at least one critical dimension error during a subsequent process to form a second semiconductor device, or during modification of the first semiconductor device is determined. The subsequent process comprises providing a semiconductor structure. The semiconductor structure comprises a photoresist layer on a semiconductor substrate. A plurality of features are formed in the photoresist layer. At least one feature of the plurality of features comprises the at least one critical dimension error.

Abstract: In a method of passivating a semiconductor device with two types of transistors, e.g., NMOS and PMOS transistor, the semiconductor device is placed in a pressurized sealed chamber and at least two different passivating gases are introduced into the chamber. The two passivating gases can be selected to have one gas suitable for passivating PMOS transistors and the other gas suitable for NMOS transistors.

Abstract: A III-V group nitride system semiconductor substrate is of a III-V group nitride system single crystal. The III-V group nitride system semiconductor substrate has a flat surface, and a vector made by projecting on a surface of the substrate a normal vector of a low index surface closest to the substrate surface at an arbitrary point in a plane of the substrate is converged on a specific point or a specific region inside or outside the plane of the substrate.

Abstract: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

Abstract: A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and treating the dielectric layer with a plasma formed from a methane-containing gas. The treating seals the exposed pores. The method includes depositing a barrier layer over the surface, the barrier layer being continuous over the sealed pores. The porous dielectric may be low K. The plasma may be formed at a bias of at least about 100 volts.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.

Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.

Abstract: A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side surfaces of the pad and a portion of the substrate adjacent to the side surfaces of the pad.

Abstract: An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

Abstract: A method and system for processing a substrate in a film removal system. The method includes providing the substrate in a substrate chamber of a film removal system, where the substrate has a micro-feature containing a dielectric film on a sidewall of the micro-feature and a photoresist film covering a portion the dielectric film, and performing a first film removal process using supercritical CO2 processing to remove the portion of the dielectric film not covered by the photoresist film. Following the first film removal process, a second film removal process using supercritical CO2 processing can be performed to remove the photoresist film. Alternately, wet processing can be used to perform one of the first film removal process or the second film removal process.

Abstract: A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysilicon layer such that an average resultant grain size of the implanted polysilicon layer after performing a pre-determined anneal is higher or lower than an average resultant grain size than would be obtained after performing the same pre-determined anneal on the polysilicon layer without a polysilicon grain size modulating species ion implant.

Abstract: A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 ? thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge.

Abstract: A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from disturbs.

Abstract: Systems and methods may provide electrical contacts to an array of substantially vertically aligned nanorods. The nanorod array may be fabricated on top of a conducting layer that serves as a bottom contact to the nanorods. A top metal contact may be applied to a plurality of nanorods of the nanorod array. The contacts may allow I/V (current/voltage) characteristics of the nanorods to be measured.

Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).

Abstract: A semiconductor doping process which enhances the dopant incorporation achievable using the Gas Immersion Laser Doping (GILD) technique. The enhanced doping is achieved by first depositing a thin layer of dopant atoms on a semiconductor surface followed by exposure to one or more pulses from either a laser or an ion-beam which melt a portion of the semiconductor to a desired depth, thus causing the dopant atoms to be incorporated into the molten region. After the molten region recrystallizes the dopant atoms are electrically active. The dopant atoms are deposited by plasma enhanced chemical vapor deposition (PECVD) or other known deposition techniques.