Abstract: A charge pump power supply for an audio power amplifier integrated circuit has an operating mode selected according to an indication of operating environment and/or a process position of the integrated circuit. The operating mode selects the output voltage provided by the charge pump and may also select efficiency by selecting a frequency of operation of the charge pump and/or the effective size of a switching transistor bank. The selection is made in conformity with an indication of a process position of the integrated circuit and/or an indication of an environment of the integrated circuit, such as temperature, power supply voltage and/or load impedance values, and generally also in conformity with a volume (gain) setting, or a detected signal level, so that internal power consumption of the amplifier and charge pump is reduced when a high signal level is not being reproduced at the audio power stage.

Abstract: An amplifier circuit includes first and second transistor circuits, a current supply unit, and a current sink unit. The first transistor circuit is operatively responsive to a first input signal, and the second transistor circuit is operatively responsive to a second input signal. The current supply unit includes at least two symmetrically configured current mirrors connected to a source voltage, and provides a first current to the first transistor circuit and a second current to the second transistor circuit, where a magnitude of the first and second currents is the same. The current sink unit is responsive to an enable signal to sink the first and second currents supplied to the first and second transistor circuits to a ground voltage.

Abstract: High-efficiency envelope tracking (ET) methods and apparatus for dynamically controlling power supplied to radio frequency power amplifiers (RFPAs). An exemplary ET circuit includes a switch-mode converter coupled in parallel with a split-path linear regulator. The switch-mode converter is configured to generally track an input envelope signal Venv and supply the current needs of a load (e.g., an RFPA). The split-path linear regulator compensates for inaccurate envelope tracking by sourcing or sinking current to the load via a main current path. A current sense path connected in parallel with the main current path includes a current sense resistor used by a hysteresis comparator to control the switching of the switch-mode converter. The split-path linear regulator is configured so that current flowing in the current sense path is a lower, scaled version of the current flowing in the main current path.

Abstract: A millimeter wave amplifier constructed on a substrate and configured for use at a frequency of 75 GHz or higher, may include four amplifier stages. A first inter-stage filter, resonant at an operating frequency of the amplifier, may couple the output of the first stage to the input of the second stage. A second inter-stage filter, resonant at the operating frequency, may couple the output of the second stage to the input of the third stage. A third inter-stage filter, resonant at the operating frequency, may couple the output of the third stage to the input of the fourth stage. A plurality of bias supply leads that couple a gate bias voltage and a drain bias voltage to each of the amplifier stages. A plurality of bias line filters, resonant at the operating frequency, may be connected from at least some of the bias supply leads to a ground plane.

Abstract: A polynomial generator and memory compensator module is provided that includes: a first bank of delay filters for generating current and delayed versions of the envelope for an RF input signal and for the square of the envelope, a polynomial generator for generating polynomials using the current and delayed versions of the envelope, each polynomial being weighted according to pre-distortion weights; an adder for adding the polynomials to provide a pre-distortion signal for pre-distorting the RF input signal to provide a pre-distorted RF input signal such that a power amplifier amplifying the pre-distorted RF input signal provides an amplified RF output signal that reduces a non-linearity of the power amplifier; and a second bank of delay filters for generating delayed versions of the output signal, wherein the adder further adds the delayed versions of the output signal to the polynomials to provide the pre-distortion signal.

Abstract: An amplifier module includes an integrated circuit device including a first amplifier circuit electrically connected to a first input terminal. The amplifier circuit includes a number of x first amplifier branches electrically connected to the first input terminal. The amplifier module also includes a number y of first output terminals each assigned to a respective TX frequency band, a first switching unit that electrically connects one or more of the first amplifier branches to one of the first output terminals, and a multilayer substrate, on top of which the integrated circuit device and the switching unit are mounted. The substrate includes integrated passive matching elements that are part of matching circuits where x?1 and y?2. Each of the first amplifier branches is adapted to deliver a different power level at its output and is matched to a load at the first output terminals by one of the matching circuits.

Abstract: Methods and systems are disclosed for closed loop feedback for pulse width modulated (PWM) switching amplifiers using predictive feedback compensation (PFC) for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude and using closed loop timing feedback. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Timing differences between pulse widths for the uncompensated PWM input signal and the pre-compensated PWM signal are used as feedback to provide closed loop width adjustment.

Abstract: The invention relates to a bypass device for a microwave amplifier unit, the microwave amplifier unit (1) comprising at least one low noise amplifier (LNA) and amplifying communication signals in at least one microwave frequency band above 500 MHz, the bypass device extending in parallel to said microwave amplifier unit (1), both extending between an input port (3) and an output port (4), in which amplifier unit (1) switching elements (9,10,16,21) for activating said bypass segment (2) in a bypass mode of the device in case said amplifier unit (1) becomes inoperable and for effectively blocking the bypass segment (2) in an active mode of the device are arranged, said bypass segment comprising a series of bypass segment sections (14,19,17) having at least one junction point connected to an associated one of said switching elements (16,21), where each of said bypass segment sections (14:19:17) comprises at least two coupled transmission lines (31,32;31,33,32;31,34,32:51,52;51,53,52:41,42;41,43,42;41,44,42), whe

Abstract: The present invention relates to balanced power amplifier network in combination with outphasing techniques such as Chireix. The object of the present invention is to provide a solution to the problem to combine balanced amplifiers like the current mode class D (CMCD) or class E/F with a LINC network. The main problem is that some power amplifiers have balanced output and the LINC network is single-ended so that a high power low loss transformer that works at several impedance levels is needed, which is hard to realize at cellular frequencies.

Abstract: A circuit arrangement for providing an analog signal is disclosed. The circuit arrangement comprises a biasing resistor; an analog input arrangement; and a signal output, wherein the biasing resistor and the analog input arrangement are connected in series between a supply voltage and a reference voltage, and the signal output is connected such that the alternating voltage over the biasing resistor is provided as an output signal. An electronic apparatus comprising such a circuit arrangement is also disclosed.

Abstract: A digitally variable gain amplifier comprising a front-end stage, a level shifter stage, and an output amplifier stage. The front-end stage comprises a high gain pre-amplifier and a low gain pre-amplifier driven in parallel by a differential input signal. A coarse gain control is realized by enabling only one pre-amplifiers at a time, while the differential input signal remains connected to the inputs of the disabled pre-amplifier. An attenuator following each pre-amplifier provides fine gain control. The enabled pre-amplifier amplifies the differential input signal and outputs a first dc voltage level. The disabled pre-amplifier is placed into a standby ready mode and outputs a second dc voltage level that is greater in magnitude than the first dc voltage level. The level shifter stage performs a minimum voltage selection operation to automatically select and level shift the amplified differential input signal, and further pass the signal to the output amplifier stage.

Abstract: An RF PA operable in two or more selectable power ranges is disclosed. Switches configure the circuit for each range such that an amplifier device corresponding to the range provides final amplification, and all lower power amplifier devices also amplify the signal. An exemplary design includes a low power amplifier configurable for operation solo, or in parallel with a medium power amplifier, to deliver an appropriately matched signal either directly to the RF PA output, or first to the input of a high power amplifier for the highest power range. The signal in all ranges of the exemplary design is conditioned in part by the matching circuitry disposed between the high power amplifier and the RF PA output, which traverses no switches in high power range operation. The entire RF PA, including switches, control and matching circuitry, is fabricated on a single monolithic integrated circuit, an achievement may be facilitated by UTSI CMOS processing.

Abstract: An electronic circuit includes: a first amplifying circuit to which a first input signal is inputted; a second amplifying circuit to which a second input signal is inputted; a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit; a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit; a common load element provided between the output node and a second power source node; a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit; and a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit.

Abstract: In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.

Abstract: One aspect of the embodiments relates to a programmable gain circuit including an amplification unit amplifying an input signal, an input resistor coupled to an input terminal of the amplification unit, a feedback resistor coupled between an output terminal of the amplification unit and the input terminal of the amplification unit, a first switch switching a resistance value of the feedback resistor, a second switch switching a resistance value of the input resistor, and a control unit controlling the second switch such that the second switch switches the resistance value of the input resistor when the first switch switches the resistance value of the feedback resistor.

Abstract: Embodiments described herein relate to amplification circuits. In some embodiments the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop. The two nested feedback loops provide a “pre-cleaning” action, which reduces the amount of rejection required in the feedforward loop. In some embodiments, the amplification circuit includes a power amplifier and an enhanced feedforward loop comprising a phase control circuit that maintains a phase balance needed to reduce distortion in the output signal of the amplification circuit. In some embodiments, the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop and the feedforward loop comprises the phase control circuit.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: A driving amplifier circuit includes: a first driver for sourcing a load current to a load; a second driver for sinking the load current from the load; a first operational amplifier (op-amp) for driving the first driver; a second operational amplifier for driving the second driver; a first bias circuit for biasing the first driver; a second bias circuit for biasing the second driver; an enabling circuit for enabling either the first bias circuit or the second bias circuit according to a control signal; a digital control circuit for monitoring currents of the first driver and the second driver to generate the control signal; and an offset equalization circuit, coupled between an internal node of the first operational amplifier and an internal node of the second operational amplifier, for adjusting DC offset of at least one of the first operational amplifier and the second operational amplifier.

Abstract: The system contains a first MOS transistor having a first source element, a first drain element, and a first gate element. A first low voltage current source has two ends. The ends of the low voltage current source are connected to at least two of the first MOS transistor elements. At least one first Zener clamp is in parallel with the low voltage current source.

Abstract: An amplifier circuit is disclosed that includes a first input terminal; a second input terminal; a first differential amplifier circuit that samples signals input to the first and second input terminals and outputs signals obtained by applying a gain to the sampled input signals having different voltages; and a second differential amplifier circuit that supplies first and second reference voltages referred to when a sampling operation is performed in the first differential amplifier circuit to the first and second input terminals, respectively. A potential difference between the first and second reference voltages is equal to an offset voltage of the first differential amplifier circuit.