Abstract: An apparatus for data processing for simultaneously performing artificial intelligence (AI) function processing and data collection and a method thereof are provided. The method of simultaneously performing AI function processing and data collection includes: receiving, by a data receiver, data; transferring, by the data receiver, the received data to a disk handler; accessing, by the disk handler, a disk in an idle state among a plurality of disks and performing writing of a file; after the writing of the file is completed, notifying, by the disk handler, a scheduler that the writing of the file is completed; transmitting, by the scheduler, job information about a job, for which the file writing is completed together with a job execution command to an AI module handler; and accessing, by the AI module handler, an AI module in an idle state among a plurality of AI modules and executing an AI function.

Abstract: Apparatuses and methods related to computer memory access determination are described. A command can be received at a memory system (e.g., a system with or exploiting DRAM). The command can comprise a memory operation and a plurality of privilege bits. The privilege level or a memory address that is associated with the memory operation can be identified. The privilege level can correspond to the memory address can describe a privilege level that can access the memory address. A determination can be made as to whether the memory operation, or the application requesting certain data or prompting corresponding instructions, is entitled to access to the memory address using the plurality of privilege bits and the privilege level. Responsive to determining that the memory operation has access to the memory address, the memory operation can be processed.

Abstract: The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.

Abstract: A memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. The primary die can communicate with an external host device and with the secondary dies. In an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. In an example, each of the secondary dies receives the same first command message.

Abstract: A persistent memory device is disclosed. The persistent memory device may include a cache coherent interconnect interface. The persistent memory device may include a volatile storage and a non-volatile storage. The volatile storage may include at least a first area and a second area. A backup power source may be configured to provide backup power selectively to the second area of the volatile storage. A controller may control the volatile storage and the non-volatile storage. The persistent memory device may use the backup power source while transferring a data from the second area of the volatile storage to the non-volatile storage based at least in part on a loss of a primary power for the persistent memory device.

Abstract: An operating method of a controller that controls a memory device, comprises: generating a data chunk including user data to be programmed in a page of the memory device and an internal parity generated by performing first ECC encoding on the user data, the internal parity being generated when a size of the user data is smaller than a size of a data area of the page, generating a page chunk including the data chunk, meta data of the user data and an external parity generated by performing second ECC encoding on the meta data and the data chunk, and controlling the memory device to program the page chunk into the page.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

Abstract: Creating a replica of a storage system, including: receiving, by a first storage system from a computing device, data to be stored on the first storage system; reducing, by the first storage system, the data using one or more data reduction techniques; sending, from the first storage system to the second storage system, the reduced data, wherein the reduced data is encrypted; and sending, from the second storage system to a third storage system, the reduced data, wherein the reduced data is encrypted.

Abstract: In a particular embodiment, a virtual namespace identifier is mapped to one or more volumes stored among a pool of storage resources, wherein at least a first storage system and a second storage system are utilized to provide the storage resources. The virtual namespace identifier is migrated among the pool of storage resources to virtualize a data path for the one or more volumes.

Abstract: A system for improving memory resource allocation efficiency for executing tasks receives a request to allocate a particular amount of memory resources to a particular database block of a database server. The system monitors the database blocks of the database server to determine whether any portion of memory resources already allocated to any of the database blocks is unutilized. If it is determined that a portion of the memory resources already allocated to any of the database blocks is unutilized, the system reallocates the unutilized memory resources to the particular database block.

Abstract: High-throughput BPF map manipulations with uprobes are disclosed. A method for manipulating a Berkeley Packet Filter (BPF) map comprises running a user program in a user space of a computing environment. The user program includes a trigger function. A corresponding kernel BPF probe is installed by the user program on the trigger function. The kernel BPF probe is triggered by reaching a memory address of the trigger function in the user space. The trigger function includes one or more arguments that the BPF map agent interprets as operation parameters. The BPF map agent performs one or more operations to manipulate a BPF map in the kernel space based on the operation parameters.

Abstract: A memory access speed adjustment method, control device and memory module are provided. The method is for use in controlling a controller of a memory and includes steps of: obtaining a current temperature value of the memory; determining an access speed threshold of the memory according to a continuous variation relation with respect to a difference between the current temperature value and a target temperature value; and adjusting, by the controller, an access speed of the memory according to the access speed threshold.

Abstract: Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

Abstract: Techniques are described for maintaining in-order execution when a dependency exists between write transactions. In some embodiments, a write re-order buffer (WROB) is configured to assign the same group ID to an incoming write transaction upon determining that the incoming write transaction is dependent on a pending write transaction. The WROB forwards the incoming write transaction to an interconnect fabric for routing to a completer device. The interconnect fabric enforces in-order execution when write transactions share the same group ID. The WROB can maintain a transaction log of pending write transactions and also track the statuses of responses for such transactions. Transaction responses can include responses sent from a completer to confirm that a transaction has actually been completed. Additionally, the WROB can send a response indicating completion back to the requester of the transaction. In some embodiments, the WROB is configured to send an early response to the requester.

Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Abstract: Methods, systems, and devices for multi-purpose signaling for a memory system are described. One or more signal paths of between a host device and a memory device may be configured to support shared pathways between multiple channels and to support multiple functions. For example, a signal path may be configured to communicate a state signal for an initialization sequence of the memory device, an error signal for the memory device to indicate that errors have occurred, or a low-power signal for the host device to request that the memory device enter a low-power mode, or a combination thereof. The signal path may be shared between two or more channels of the memory device.

Abstract: In one embodiment, a method comprises maintaining state information regarding a data synchronous replication status for a storage object of a primary storage cluster and a replicated storage object of a secondary storage cluster. The method includes temporarily disallowing input/output (I/O) operations for the storage object when the storage object of the primary storage cluster has a failure, which causes an internal state as out of sync for the storage object while maintaining an external state as in sync for external entities. The method performs persistent inflight tracking and reconciliation of I/O operations with a first Op log of the primary storage cluster and a second Op log of the secondary storage cluster and performs a resynchronization between the storage object and the replicated storage object based on the persistent inflight tracking and reconciliation of I/O operations.

Abstract: Various examples are directed to a host device comprising a memory system, a host device memory, and a processor. The processor is programmed to receive from the memory system a first logical-to-physical (L2P) pointer message that comprises a first L2P pointer and a first digital signature. The processor executes a cryptographic operation based at least in part on the first L2P pointer and a cryptographic key and verifies the first digital signature based at least in part on the cryptographic operation. The processor caches the first L2P pointer at the host device memory.

Abstract: According to one embodiment, a controller constructs a plurality of block groups. The plurality of block groups include at least a first block group configured using a first type block group and a second block group configured using a second block group. The first type block group includes a plurality of non-defective blocks obtained by selecting one or more non-defective blocks in an equal number from each of a plurality of dies or each of a plurality of planes. The second type block group includes a plurality of non-defective blocks. The number of non-defective blocks included in the second type block group is equal to the number of non-defective blocks included in the first type block.

Abstract: A memory device configured to descramble scrambled composite data. In one approach, the scrambled composite data is provided by an XOR (exclusive OR operation) of more than one data set scrambled with non-linear scramblers. A memory device is configured to receive scramble codes generated by non-linear scramblers and perform an XOR of the scrambled composite data with the scramble codes to remove scrambling from the composite data. In one example, the scrambled data sets are data to be written to a NAND device at more than one bit per cell density (e.g., MLC, TLC, QLC, PLC, etc.). For example, the scrambled data sets may be written to the NAND device in more than one programming pass. In one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.