Abstract: According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The final stage die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a first transistor. The driver stage die includes another type of semiconductor substrate (e.g., a silicon substrate), a second transistor, and one or more secondary circuits that are electrically coupled to a control terminal of the first transistor. A connection (e.g., a wirebond array or other DC-coupled connection) is electrically coupled between an RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. The secondary circuit(s) of the driver stage die include a final stage bias circuit and/or a final stage harmonic control circuit, which are electrically connected to the final stage die through various connections.

Abstract: Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Abstract: An embodiment provides an amplifier system with multiple amplification paths connected to a combiner for combination of signals amplified in the amplification paths, each amplification path comprising an amplifier and a matching network provided between the amplifier and the combiner, wherein the individual amplifiers can interact through the combiner, causing an active load-pull effect. The matching networks of the paths comprise harmonic terminations configured to one or more of reduce an overlap between the voltage and current waveforms within the amplifier connected to the matching network and improve the linearity of one or more of the amplifiers.

Abstract: Thermally rugged power amplifiers and related methods. In some embodiments, a method for manufacturing a radio-frequency amplifier can include providing or forming a semiconductor substrate, and forming an array of cascoded devices on the semiconductor substrate to be capable of amplifying a signal, such that the array of cascoded devices includes a plurality of cascoded devices arranged in a first row and a plurality of cascoded devices arranged in a second row. Each cascoded device can include an input stage and an output stage arranged in a cascode configuration, and each of the first and second rows can be configured such that the output stages are positioned in a staggered orientation. The staggered arrangement of the cascoded devices in the first row can be offset relative to the staggered arrangement of the cascoded devices in the second row to avoid a direct row-to-row adjacent pair of output stages.

Abstract: An amplifier assembly includes a three or more way Doherty amplifier arrangement (DAA) having at least three amplifiers, including a main amplifier and at least two peak amplifiers. The DAA is within a dual-path package including a first-RF-input-lead and a second-RF-input-lead for receiving components of a split RF-input signal and providing the components to the DAA. A first-RF-output-lead and a second-RF-output-lead receive a split output signal from the DAA. The DAA includes a first-semiconductor-die and a second-semiconductor-die, each having thereon respective amplifier(s). The first-semiconductor-die includes a Doherty-splitter element splitting the RF-input signal from the first-RF-input-lead to provide an input to two amplifiers thereon and a Doherty-combiner element to combine an output from the two amplifiers. The Doherty-combiner element is connected to the first-RF-output-lead.

Abstract: An embodiment of a Doherty amplifier includes first and second amplifier paths with first and second amplifiers, respectively, a power divider, a series delay element, and a short-circuited stub. The power divider is configured to receive a radio frequency (RF) signal and to divide the RF signal into first and second input signals that are produced at first and second power divider outputs. The series delay element is coupled between the first power divider output and the first amplifier. The short-circuited stub is coupled between the first power divider output and the first amplifier or between the second power divider output and the second amplifier. The first amplifier path is characterized by a first frequency-dependent insertion phase, the second amplifier path is characterized by a second frequency-dependent insertion phase, and a slope of the first or second frequency-dependent insertion phase is altered by the short-circuited stub.

Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.

Abstract: Systems and methods are disclosed for a multi-mode radiofrequency (RF) module comprising a semiconductor die and a power amplifier residing on the die. The power amplifier is configured to operate in a first RF mode corresponding to a first RF wireless technology standard and a second RF mode corresponding to a second RF wireless technology standard. A first set of circuitry within the power amplifier is active in the first RF mode and a second set of circuitry within the power amplifier is active in the second RF mode.

Abstract: A composite power amplifier for amplification of an input signal into an output signal is disclosed. The composite power amplifier comprises an input port for receiving the input signal, and an output port for providing the output signal. Furthermore, the composite power amplifier comprises a first set of sub-amplifiers, comprising at least two sub-amplifiers, wherein the at least two sub-amplifiers are arranged along a taper of a first transmission line, wherein the first transmission line is connected to the first set of sub-amplifiers and the output port. Moreover, the composite power amplifier comprises a second set of sub-amplifiers, comprising at least two sub-amplifiers, wherein the at least two sub-amplifiers are arranged along a taper of a second transmission line, wherein the second transmission line is connected to the second set of sub-amplifiers and the output port.

Abstract: A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

Abstract: An amplifier arrangement comprises N amplifier stages (101 to 10N). The amplifier arrangement comprises a main cascade of quarter wavelength transmission lines coupled between an output of a main amplifier (102) of the N amplifier stages (101 to 10N) and an output node (15) of the amplifier arrangement, wherein the main cascade comprises N?1 quarter wavelength transmission lines (111 to 11N-1). An output of one peaking amplifier (10N) of the N amplifier stages is coupled to the output node (15), and remaining peaking amplifiers (101, 103 to 10N-1) of the N amplifier stages coupled to respective junctions (121 to 12N-2) in the main cascade of quarter wavelength transmission lines (111 to 11N-1).

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

Abstract: An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier with a feedback capacitor; a switch that drives charging and discharging of the feedback capacitor; an additional capacitor; and a coupling circuit, which alternatively connects the additional capacitor in parallel to the feedback capacitor or else decouples the additional capacitor from the feedback capacitor. The switch opens at a first instant, where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor from the feedback capacitor in a way synchronous with a second instant, where the first component assumes a second zero value.

Abstract: A power amplification circuit includes: a first amplifier that is input with a first signal and outputs a second signal; a bias circuit that supplies a bias current or voltage to the first amplifier; and a control voltage generating circuit that generates a control voltage in accordance with the first signal. The bias circuit includes a first transistor that outputs the bias current or voltage, a second transistor provided between the emitter or source of the first transistor and ground, and a third transistor that is supplied with the control voltage and that supplies a first current or voltage to the second transistor. The value of the first current or voltage when the signal level is a first level is larger than the value of the first current or voltage when the signal level is a second level. The first level is higher than the second level.

Abstract: An adaptive bias circuit for a power amplifier may include a terminal node coupled to the power amplifier. The adaptive bias circuit may also include a low impedance bias circuit coupled to the terminal node. The adaptive bias circuit may further include a high drive bias circuit coupled to the low impedance bias circuit through the terminal node. A separation device may be arranged between the low impedance bias circuit and the high drive bias circuit.

Abstract: Systems, circuits and methods related to dynamic error vector magnitude (DEVM) corrections. In some embodiments, a power amplifier (PA) system can include a PA circuit having a plurality of amplification stages, and a bias system in communication with the PA circuit and configured to provide bias signals to the amplification stages. The PA system can further include a first correction circuit configured to generate a correction current that results in an adjusted bias signal for a selected amplification stage, with the adjusted bias signal being configured to compensate for an error vector magnitude (EVM) during a dynamic mode of operation. The PA system can further include a second correction circuit configured to change the correction current based on an operating condition associated with the PA circuit.

Abstract: The present invention is directed to electrical circuits and techniques thereof. More specifically, an embodiment of the present invention provides a variable gain amplifier that includes a first transistor and a second transistor whose gate terminals are coupled to a first input terminal. A first drain terminal of the first transistor and a first source terminal of the second transistor is coupled to a voltage gain control switch. There are other embodiments as well.

Abstract: A millimeter (mm) wave power amplifier includes a plurality of amplifiers, each amplifier including an amplifying FET including a gate, drain and source. The mm wave power amplifier also includes an input port, an output port, a VDS port being connected to a VDS voltage source for setting the drain-source voltage of the FET, and a VGS port being connected to a VGS voltage source for setting the gate-source voltage of the FET. The output ports of the amplifiers are connected to a signal combiner and the input ports of the amplifiers are connected to a signal splitter. At least one of (a) at least two of the VGS ports are connected to different VGS voltage sources, and (b) at least two of the VDS ports are connected to different VDS voltage sources.