Abstract: The present disclosure provides a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a gate layer, a source and a drain located on the gate layer, and an active layer located on the source and the drain. The active layer is electrically connected to the source and the drain. The active layer comprises two sides arranged in parallel, and each side forms an acute angle of 45° with a face of the drain facing the source.

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

Abstract: A light-emitting device including a substrate, three-dimensional semiconductor elements resting on the substrate, at least one shell at least partially covering the lateral walls of the semiconductor element, the shell including an active area having multiple quantum wells, and an electrode at least partially covering the shell, at least a portion of the active area being sandwiched between the electrode and the lateral walls of the semiconductor element. The active area includes an alternation of first semiconductor layers mainly including a first element and a second element and of second semiconductor layers mainly including the first element and the second element and further including a third element. In at least three of the layers, the mass concentration of the third element increases in the portion of the active layer as the distance to the substrate decreases.

Abstract: A device including a biopolymer membrane, a passivation layer on the biopolymer membrane, a graphene layer on the passivation layer, a source electrode on the graphene layer, and a drain electrode on the graphene layer, wherein the graphene layer extends between the source electrode and the drain electrode.

Abstract: A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

Abstract: Described herein is a technique capable of improving the controllability of a thickness of a film formed on a large surface area substrate having a surface area greater than a surface area of a bare substrate and improving the thickness uniformity between films formed on a plurality of large surface area substrates accommodated in a substrate loading region by reducing the influence of the surface area of the large surface area substrate and the number of the large surface area substrates due to a loading effect even when the plurality of large surface area substrates are batch-processed using a batch type processing furnace.

Abstract: A light-emitting device includes a substrate including a top surface and a first side surface, wherein an area of the top surface is larger than an area of the first side surface, and a light-emitting structure on the first side surface of the substrate, the light-emitting structure having a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer, wherein the light-emitting structure emits a first light having a first peak wavelength, and wherein an emission area of a first light emitted through the top surface of the substrate is larger than an emission area of a first light emitted through the first side surface of the substrate.

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to a method of forming vertical channel devices. In one aspect, a method of forming vertical channel devices includes providing a semiconductor structure that includes a substrate and a plurality of vertical channel structures. The method additionally includes surrounding the vertical channel structures with respective wrap-around gates. The method additionally includes forming enlarged top portions by selectively growing a doped semiconductor material on respective top portions of at least a subset of the vertical channel structures. The method further includes forming a top electrode on each of the enlarged top portions.

Abstract: The present invention relates to methods and apparatuses for using head waves to greatly improve microseismic event localization accuracy, particularly in the depth dimension, by analyzing them in addition to direct path arrivals whenever they are observed. Embodiments of the invention also include techniques known as multipath analysis.

Abstract: A radio frequency module includes a wiring substrate, a plurality of components mounted on an upper surface of the wiring substrate, a sealing resin layer laminated on the upper surface of the wiring substrate and covering the plurality of components, a groove formed in an upper surface of the sealing resin layer and extending between predetermined components of the plurality of components, and a shielding wall made of conductive paste in the groove. The sealing resin layer has a stepped area defining the higher portion and lower portion in the upper surface. The groove intersects the stepped area when the wiring substrate is seen in plan view.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: The present disclosure relates to a solid state image sensor, a fabrication method, and an electronic apparatus, which enable to efficiently provide trench structures, which surrounds respective pixel sections of the solid state image sensor, and through-electrodes side by side. A solid state image sensor according to a first aspect of the present disclosure includes photoelectric conversion sections formed in respective pixel sections of a semiconductor substrate, trench structures defined by walls of insulating films formed in a depth direction of the semiconductor substrate and surrounding the respective pixel sections, and through-electrodes formed through the semiconductor substrate at positions overlapping the respective trench structures. The present disclosure can be applied, for example, to back-side illumination CMOS image sensors.

Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.

Abstract: An LED package allows a fluorescent material to be uniformly distributed around an LED chip on a base when a filling space inside a transparent wall surrounding the LED chip is filled with the fluorescent material. The LED package includes a base, at least one LED chip mounted on the base, a transparent wall formed on the base and having a filling space around the LED chip, and a fluorescent material, with which the filling space is filled to cover the LED chip.

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a substrate and a first fin structure and a second fin structure over the substrate. The semiconductor device also includes a first gate stack and a second gate stack partially covering the first fin structure and the second fin structure, respectively, and a stack structure over the substrate. The stack structure is between the first gate stack and the second gate stack. The stack structure includes a semiconductor layer over the substrate and a protection layer over the semiconductor layer.

Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.

Abstract: A high voltage transistor with low on resistance is disclosed. The transistor may include at least one cut out region in the drift region under the drain of the transistor. The cut out region is devoid of the drift well which connects the drain to the channel. Cut out regions may be distributed along the width direction of the drain region of the transistor. The transistor may alternatively or further include a vertical polysilicon plate surrounding the device region. The vertical polysilicon plate may be implemented as a deep trench isolation region. The deep trench isolation region includes a deep trench lined with an insulation collar and filled with polysilicon. The vertical polysilicon plate reduces an on resistance to improve device performance.