Abstract: According to one embodiment, a semiconductor memory device includes a first cell region including a plurality of memory cells, a second cell region including a plurality of memory cells, a connection region between the first cell region and the second cell region, and a row decoder for propagating a voltage to word lines in the first and second cell regions via the connection region.

Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.

Abstract: A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

Abstract: An integrated device package is disclosed. The integrated device package can include a package housing that defines a cavity. The integrated device package can include an integrated device die that is disposed in the cavity. The integrated device die has a first surface includes a sensitive component. A second surface is free from a die attach material. The second surface is opposite the first surface. The integrated device die include a die cap that is bonded to the first surface. The integrated device package can also include a supporting structure that attaches the die cap to the package housing.

Abstract: A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

Abstract: A module that improves heat-dissipation efficiency and can prevent a warp and a deformation of the module is provided. A module includes a substrate, a first component mounted on an upper surface of the substrate, a heat-dissipation member, and a sealing resin layer that seals the first component and the heat-dissipation member. The heat-dissipation member is formed to be larger than the area of the first component when viewed in a direction perpendicular to the upper surface of the substrate and prevents heat generation of the module by causing the heat generated from the first component to move outside the module. The heat-dissipation member has through holes, and the through holes are packed with a resin, which can prevent the sealing resin layer from peeling off.

Abstract: A sensor includes: a redistribution layer comprising a first face and a second face opposite to each other; a first die electrically connected to the first face of the redistribution layer; a molding compound comprising a third face and a fourth face opposite to each other, wherein the third face of the molding compound is combined with the first face of the redistribution layer, and the molding compound encapsulates the first die on the side of the first face of the redistribution layer; and a sensing element electrically connected to the redistribution layer. The package assembly of the sensor allows more elements to be packaged together, and provides a better structural support or provides a better heat distribution for the package assembly, and at the same time, reduces the volume and costs of the entire package assembly.

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

Abstract: Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.

Abstract: An imaging element includes a photoelectric conversion unit including a first electrode 11, a photoelectric conversion layer 13, and a second electrode 12 that are stacked, in which the photoelectric conversion unit further includes a charge storage electrode 14 arranged apart from the first electrode 11 and arranged to face the photoelectric conversion layer 13 through an insulating layer 82, and when photoelectric conversion occurs in the photoelectric conversion layer 13 after light enters the photoelectric conversion layer 13, an absolute value of a potential applied to a part 13C of the photoelectric conversion layer 13 facing the charge storage electrode 14 is a value larger than an absolute value of a potential applied to a region 13B of the photoelectric conversion layer 13 positioned between the imaging element and an adjacent imaging element.

Abstract: A semiconductor device includes a dielectric layer having a first surface and a second surface opposite to the first surface; an active region on the first surface of the dielectric layer; a power rail under the second surface of the dielectric layer, wherein the dielectric layer is between the active region and the power rail; a spacer physically dividing the active region into a first part and a second part, the first part and the second part being conductively isolated from each other by the spacer; an intermediate layer comprising: first and second conductive segments; and wherein the spacer joins the first conductive segment and the second conductive segment, and electrically isolates the first conductive segment from the second conductive segment, wherein a join length between the first conductive segment and the spacer is equal to a join length between the second conductive segment and the spacer.

Abstract: A nanobio-sensing device includes: a substrate; a source electrode and a drain electrode which are disposed on the substrate and spaced apart from each other; a sensing film which serves as a channel connecting the source electrode and the drain electrode and is in contact with at least a part of the source electrode and the drain electrode; a first gate electrode which is a floating gate, extends while one end of the first gate electrode is in contact with a part of the sensing film, and is capable of being in contact with a part of the source electrode and/or the drain electrode; and a second gate electrode which is in contact with the other end of the first gate electrode to form a first gate stacked structure.

Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

Abstract: A MEMS sensor includes a silicon substrate that has a first surface and a second surface on a side opposite to the first surface and that has a cavity in the first surface, a silicon diaphragm that has a first surface and a second surface on aside opposite to the first surface and in which the second surface is joined directly to the first surface of the silicon substrate, and a piezoresistance formed at the first surface of the silicon diaphragm, and, in the MEMS sensor, a plane orientation of the first surface of the silicon substrate and a plane orientation of the first surface of the silicon diaphragm differ from each other.

Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.