Abstract: A storage service supports attachment of multiple clients to a distributed storage object and further supports persistent reservations that govern types of access the respective clients are granted with respect to the distributed storage object. In order to efficiently distribute reservation state changes to multiple partitions of the distributed storage object hosted by different data storage units/servers, existing connections are used between the data storage units/servers hosting the partitions of the distributed storage object and the connected clients to propagate reservation state changes.

Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and an interconnect fabric coupled to the system memory and the multiple vertical cache hierarchies. Based on a request of a requesting processor core among the plurality of processor cores, a master in the multiprocessor data processing system issues, via the interconnect fabric, a read-type memory access request. The master receives via the interconnect fabric at least one beat of conditional data issued speculatively on the interconnect fabric by a controller of the system memory prior to receipt by the controller of a systemwide coherence response for the read-type memory access request. The master forwards the at least one beat of conditional data to the requesting processor core.

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described. A hierarchical memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. Logic circuitry can be configured to determine that a request to access a persistent memory device corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device. Access data and control messages can be transferred between or within a memory device, including to or from a multiplexer and/or a state machine. A state machine can include logic circuitry configured to transfer interrupt request messages to and receive interrupt request messages.

Abstract: A semiconductor device and the like for maintaining a required function while suppressing unauthorized accesses are provided. The semiconductor device 100 includes a main control device 110 and a sub-control device 120. The main control device 110 includes a main memory 112 for storing main programs for receiving external signals, and a trigger signal output circuit 115 for outputting a trigger signal when an abnormal signal process differs from preset signal processing is performed. The sub-control device 120 is coupled to the main control device 110, and includes a trigger signal obtaining circuit 121 for obtaining a trigger signal, and a sub-program outputting circuit 123 for outputting a sub-program to the main control device 110 based on the obtained trigger signal.

Abstract: Disclosed herein is an apparatus for managing disaggregated memory, which is located in a virtual machine in a physical node. The apparatus is configured to select, depending on the proportion of valid pages, direct transfer between remote memory units or indirect transfer via local memory for each of the memory pages of the source remote memory to be migrated, among at least one remote memory unit used by the virtual machine, to transfer the memory pages of the source remote memory to target remote memory based on the direct transfer or the indirect transfer, and to release the source remote memory.

Abstract: A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.

Abstract: A storage system includes a storage device and a host device. The storage device includes a nonvolatile memory device having a first size and a first volatile memory device having a second size smaller than the first size and configured to operate as a cache memory with respect to the nonvolatile memory device. The first volatile memory device is configured to allow a first bus portion access to cache data stored in the first volatile memory device. The host device is configured to generate a cache table corresponding to information in the cache data stored in the first volatile memory device and configured to read the cache data stored in the first volatile memory device via the first bus portion based on the cache table.

Abstract: The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

Abstract: The present disclosure provides a method of logical to physical mapping for a data-storage device comprising a non-volatile memory device. The method comprises maintaining a first type of information representing at least a part of a logical-to-physical address translation map. Further, the method comprises maintaining a second type of information pertaining to the logical-to-physical translation map as a part of a physical page. Further, the method comprises completing a logical-to-physical mapping based on the first and second type of information to thereby determine a physical location, within one or more of the physical pages, of the data stored in each logical page.

Abstract: Methods, systems, and devices associated with techniques for secure writes by non-privileged users are described. A memory device may be configured with one or more blocks of memory operating in a secure write mode. The memory device may receive an append command from a non-privileged user. The append command may indicate data to write to the block of memory at an address determined by the memory device. The memory device may identify a pointer to the address for storing the data within the block of memory. The memory device may write the data to a portion of the block of memory based on identifying the pointer and may update the pointer associated with the block of memory based on writing the data.

Abstract: According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.

Abstract: Systems, apparatus and methods are provided for logical-to-physical (L2P) address translation. A method may comprise receiving a request for a first logical data address (LDA), and calculating a first translation data unit (TDU) index for a first TDU. The first TDU may contain a L2P entry for the first LDA. The method may further comprise searching a cache of lookup directory entries of recently accessed TDUs using the first TDU index, determining that there is a cache miss, generating and storing an outstanding request for the lookup directory entry for the first TDU in a miss buffer, retrieving the lookup directory entry for the first TDU from an in-memory lookup directory, determining that the lookup directory entry for the first TDU is not valid, reserve a TDU space for the first TDU in a memory and generating a load request for the first TDU.

Abstract: A computer-implemented method according to one embodiment includes identifying a request to migrate data associated with a volume from a source storage pool having a first rank extent size to a destination storage pool having a second rank extent size smaller than the first rank extent size, creating a correspondence between logical volume extents of the volume and physical offset locations within rank extents of the source storage pool, and migrating data from one or more ranks of the source storage pool to one or more ranks of the destination storage pool, utilizing the correspondence between the logical volume extents of the volume and the physical offset locations within the rank extents of the source storage pool.

Abstract: A storage device includes a nonvolatile memory including a plurality of first blocks having memory cells each configured to store one bit of data and a plurality of second blocks having memory cells each configured to multiple bits of data; and a controller configured to determine whether or not a number of use-completed second blocks, each of which has a first threshold number or less of valid pages, among use-completed second blocks of the plurality of second blocks, is equal to or larger than a second threshold number and to select, according to a determination result, a victim block on which garbage collection is to be performed among used-completed first blocks of the plurality of first blocks or the use-completed second blocks each having the first threshold number or less of valid pages.

Abstract: A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents propagation of the dead data to other levels of memory in response to eviction of the dead data or flushing of the cache at which the dead data is stored.