Abstract: A clock signal reproduction circuit including an A/D conversion circuit for converting an input RF analog signal with a restricted upper limit of a frequency band into a digital signal, a digital phase error calculation unit for digitally calculating a phase error of a digital signal converted in the A/D conversion circuit, a control voltage generating unit including a loop filter, a D/A conversion unit for outputting an analog control voltage signal based on the digital phase error calculated, and an analog voltage-controlled type oscillating circuit for outputting a reproduction clock signal having a frequency of at least 2 times the frequency of the input analog signal. The A/D conversion circuit uses the clock signal output from the analog voltage-controlled type oscillating circuit to convert the input analog signal into a digital format and output a reproduction clock signal from the analog voltage-controlled oscillating circuit.

Abstract: A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively.

Abstract: A method and apparatus for estimating a frequency of a received carrier wave in a Quadrature Phase Shift Keying (QPSK) system. The invention uses a combination of an FFT, DFT bins, and three point interpolation to estimate a frequency of the carrier wave. The system is robust and compensates for multipath fading and other types of signal degradation.

Abstract: A method for demodulating a received spread-spectrum signal using a minimum-shift-keyed (MSK) receiver. Using the method, an in-phase-component signal and a quadrature-phase-component signal are generated from a received spread-spectrum signal. The in-phase-component signal and the quadrature-phase-component signal are then processed and combined in such a way as to estimate data of the received-spread-spectrum signal.

Abstract: A PLL circuit includes a PLLic formed into an integrated circuit; a loop filter for receiving an output signal from the PLLic; a voltage-controlled oscillator having an oscillation frequency which is controlled according to an output signal of the loop filter for applying a controlled oscillation output signal to the PLLic, the voltage-controlled oscillator including a resonator and a negative resistor circuit; wherein a buffer amplifier functioning as a part of the voltage-controlled oscillator is incorporated into the PLLic, and the resonator and the negative resistor circuit of the voltage-controlled oscillator are disposed outside of the PLLic.

Abstract: A timing recovery apparatus for recovering the timing from sparse timing information in multi-level or partial response codes. The timing recovery apparatus includes a switch for sampling an incoming line code signal according to a selectable sample rate, a feed forward equalizer for filtering the sampled signal, a decision feedback equalizer for cancelling intersymbol interference in the filtered signal and for recovering the timing in the sampled signal. The timing recovery circuit creates a phase correction signal in response to a signal received from the feed forward equalizer and thereby control the sample rate of the sample switch so that the signal-to-noise ratio at the node before the decision is maximized. The voltage controlled crystal oscillator may be controlled within a certain frequency range by using a second phase detector which compares the phase of the signal controlling the sampling of the incoming line code with a reference clock.

Abstract: A carrier tracking loop that uses a frequency locked loop (FLL) and incorporates synchronized matched filters to minimize complexity of the system. The synchronized matched filters eliminate out-of-band interference while minimizing computation. The carrier tracking loop has an improved error signal generation to extend a frequency range and by employing error signal normalization, which extends the dynamic range of the amplitude of the input signal and allows the frequency to flywheel when signal fading occurs.

Abstract: A communication and/or measurement system includes a transmitter that modulates a pseudo-random noise signal with a message signal to produce a wideband signal for transmission. A receiver, which demodulates the wideband signal to recover the message signal, includes an "analog" feedback shift register that reproduces the noise signal based on samples of the received signal. The AFSR is characterized by a function that agrees with the function that characterizes the LFSR, at the points at which that function is defined. Further, the AFSR characterizing function has stable fixed points at these values, i.e., it has a slope of less than one in these regions. Specifically, the AFSR's function has stable fixed points at integer values and unstable fixed points at half-integer values and, the stable fixed points act as attractors. The AFSR thus produces a sequence that relaxes to the nearest integer-valued sequence.

Abstract: A clock signal generation circuit performs a stable operation with respect to both a high frequency input clock signal and a sufficient low frequency testing clock signal.

Abstract: A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

Abstract: An adaptive equalizer decision circuit for a digital television signal, including a field synchronizing signal, consisting of multilevel symbols and a DC offset representing a pilot. The variation of the DC level of the received signal during the field sync with respect to a predetermined threshold is derived for placing the equalizer in a training signal or data directed operating mode. Another approach determines the difference between a current value of the field sync and each of a plurality of values of the field sync in previous fields and determining therefrom whether the equalizer should be in its data directed mode of operation or in its training signal mode of operation. A modification consists in controlling the step size of the equalizer based upon either the DC level variation or the field sync differences of the received signal. The modification may be used alone or in combination with the equalizer operating mode control.

Abstract: A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively.

Abstract: A second order PLL uses on-chip dynamically configurable compensation to permit varying loop bandwidth and damping ratio simultaneously in response to command signals. In a first embodiment, a type 2 PLL is compensated by synthesizing a two-pole lowpass filter, a zero, and a gain-programmable integrator. By appropriate selection of transfer function characteristics associated with each of these three building blocks, the open loop PLL transfer function may be remotely varied by scaling resistance or transconductance. In a second embodiment, a type 2 PLL is compensated using a simple series R-C in parallel with C configuration, wherein component selection results in a transfer function that permits relocation of a zero and a pole by varying a single resistance or transconductance. Such variation is preferably accomplished using ganged banks of resistors, remotely switched by associated metal-on-silicon transistors.

Abstract: A QPSK demodulator symbol tracking loop including automatic noise normalization and reacquisition control enables improved symbol tracking and acquisition during fading or intermittent channel conditions. A noise variance estimate is determined and the symbol tracking loop flywheels when the signal level dips below a flywheel threshold relative to the noise variance estimate during fading or intermittent channel conditions. Determination in advance of an absolute power level of the thermal noise floor of analog front end components is dispensed with and precise control of the gain and noise level of the analog front end components is not needed, thus simplifying design. A reacquisition mode is declared upon determination of an abrupt increase in signal level indicative of emergence from a fading condition or upon detection of an excessive symbol tracking error signal. During the reacquisition mode, the loop gain of the symbol tracking loop is temporarily increased to improve reacquisition time.

Abstract: A phase-locked loop circuit recovering original clock information and original stream of binary data both from Manchester-coded data is disclosed. The phase-locked loop circuit comprises first, second, and third exclusive-OR circuits each with two inputs and an output. The phase-locked loop circuit further comprises a controlled oscillator that generates two local clock signals that are phase shifted from each other, preferably by an amount of 90.degree., with the first being at 0.degree. phase shift. The 0.degree. clock signal is applied to one input of the first exclusive-OR circuit having Manchester-coded data at its other input. The 90.degree. phase shifted clock is applied to one input of the second exclusive-OR circuit having Manchester-coded data at its other input. The output of each of the first and second exclusive-OR circuits, after passing through associated circuitry, is applied to the third exclusive-OR circuit.

Abstract: A variable length code (VLC) decoding apparatus for decoding sequential variable length codewords includes a second barrel shifter cascaded to a first barrel shifter for providing a second table memory device with a decoding window output sequence which is directly shifted in response to a codeword length output from a first table memory device so that the first bit in the decoding window output sequence is the first bit of the next variable length codeword in a decoding window output sequence from the first barrel shifter; and the second table memory device for producing a fixed length codeword in response to each variable length codeword in the second decoding window output sequence, to thereby decode, at each clock cycle, consecutively two variable length codewords without an operational delay in an accumulator for shifting the decoding window of the first barrel shifter.

Abstract: An equalizer is provided for enhancing the recoverability of digital audio broadcasting signal information. The equalizer receives the AM compatible digital audio broadcasting waveform and stores that waveform as a waveform vector. The equalizer then processes that waveform by multiplying the waveform vector by an equalization vector. This equalization vector comprises a plurality of equalizer coefficients, each of the coefficients initially set to a predetermined value. The equalizer then compares each location of the processed waveform vector with a stored waveform vector. The equalizer selects as the signal that vector location closest to the stored waveform vector. Preferably, the equalizer includes means for updating the equalizer coefficients using the waveform vector, the processed waveform vector, and the stored waveform vector to provide immunity to noise.

Abstract: A phase lock loop circuit that can be formed into a full monolithic integrated circuit without an external component part, and that can maintain the phase locked state even for a consecutive identical bit state of input data including more than several tens of consecutive identical bits. The input data applied to a data input terminal is doubled in frequency by a doubler. A phase difference between the output of the doubler and that of a VCO is detected by a phase comparator, and is supplied to a low-pass filter through a sample and hold switch circuit. The low-pass filter produces a DC output corresponding to the phase difference, and supplies it to the frequency control terminal of the VCO. The output frequency of the VCO is controlled so that the phase difference becomes zero.

Abstract: First, an adaptive filter 15 provided in a reflective wave detection unit 13 performs an adaptive operation on a digital signal inputted to an input terminal 10 for eliminating a multipath component from the digital signal. Also, a filter update unit 21 updates filter coefficient for a digital filter 18 comprising an FIR filter of lower degree. After the elapse of a predetermined time, reflective wave estimation unit 16 estimates reflection coefficient and delay time of a reflected wave contained in the digital signal from a filter coefficient at that point of time, and outputs the estimated values to a controller 14. Based on the input estimated values, the controller 14 initializes a delay time of a delay element of a digital filter 23 comprising an IIR filter of first degree of a multipath eliminating adaptive filter 11 and a multiplication coefficient of a multiplication element of the same.

Abstract: A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected.