Abstract: A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described herein, includes tracking one or more factors relating to a plurality of data sets, evaluating the plurality of data sets based on the one or more factors. The evaluating may include speculating at least one of relevancy and accessibility of each of the plurality of data sets. The method may further include generating data scores, the data scores being associated with the plurality of data sets based on the evaluation of the plurality of data sets, performing a first comparison of the data scores of the plurality of data sets with a criteria score, and classifying each data set based on the first comparison. The classifying may include setting caching order for each data set of the plurality of data sets.

Abstract: Data processing includes accessing a product category tree, the product category tree comprising a plurality of hierarchical levels. A leaf category level of the plurality of hierarchical levels comprises a leaf category node. The leaf category node includes product information. The product information comprises a plurality of product attribute parameters. The plurality of product attribute parameters comprises standard product information. Data processing further includes selecting, among the plurality of product attribute parameters that correspond to the leaf category node, a representative product attribute parameter that is representative of the product information; and partitioning standard product information of the leaf category node to obtain a plurality of sets using the representative product attribute parameter, wherein each of the plurality of sets includes at least some of the standard product information.

Abstract: A system to collect and store in a special data structure arranged for rapid searching massive amounts of data. Performance metric data is one example. The performance metric data is recorded in time-series measurements, converted into unicode, and arranged into a special data structure having one directory for every day which stores all the metric data collected that day. The data structure at the server where analysis is done has a subdirectory for every resource type. Each subdirectory contains text files of performance metric data values measured for attributes in a group of attributes to which said text file is dedicated. Each attribute has its own section and the performance metric data values are recorded in time series as unicode hex numbers as a comma delimited list. Analysis of the performance metric data is done using regular expressions.

Abstract: A method of fabricating silicon TFTs (thin-film transistors) is disclosed. The method comprises a crystallization step by laser irradiation effected after the completion of the device structure. First, amorphous silicon TFTs are fabricated. In each of the TFTs, the channel formation region, the source and drain regions are exposed to laser radiation illuminated from above or below the substrate. Then, the laser radiation is illuminated to crystallize and activate the channel formation region, and source and drain regions. After the completion of the device structure, various electrical characteristics of the TFTs are controlled. Also, the amorphous TFTs can be changed into polysilicon TFTs.

Abstract: A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer.

Abstract: In an HEMT, a channel forming layer is arranged above a semi-insulating substrate via a buffer layer. A spacer layer is arranged on the channel forming layer and an electron supplying layer and a Schottky contact layer are sequentially arranged on the spacer layer. A diffusion preventing layer, for preventing a metal element of a gate electrode from diffusing into the channel forming layer, is arranged in the Schottky contact layer.

Abstract: A light-emitting diode chip having an anode electrode and a cathode electrode both arranged on its top surface is placed in a cavity formed in a base board that has conductors so laid as to extend from its top surface to its bottom surface. The anode and cathode electrodes are connected, by way of wires, to the conductors laid on the top surface of the base board, respectively, and then the light-emitting diode chip and the wires are sealed in a resin mold. The electrodes are situated at a level equal to or higher than the top surface of the base board so that the wires can be fixed on the electrodes without interference between the wire-bonding tool and the base board.

Abstract: Isolation structures and means for isolating the electron injectors in an organic light emitting device are disclosed. The isolation structures may reduce the likelihood of electrical shorts or cross-talks between adjacent columns of electron injector material. The isolation structures may comprise multiple layers of distinct material, including a layer of organic insulation material, such as photoresist or other hydrophobic organic material. The insulation material may be spin or extrusion coated onto the device. The insulation material may be sandwiched between inorganic oxide layers. The insulation material may be selected such that it is capable of being preferentially etched relative to the oxide layers by dry etching methods such as oxygen plasma. Alternatively, the insulation material may be made of material that does not have a very strong adhesion to an underlying oxide layer, so that the insulation material and any conductive material formed on top of it may be removed using a tape lift-off process.

Abstract: At the time of forming an alloy composition gradient layer 4 of gallium arsenide phosphide GaAs.sub.x P.sub.1-x having an arsenic alloy composition x changed in such a range as not to exceed a predetermined alloy composition a with an increase of a layer thickness d between a GaP layer 3 and a composition constant layer 5 of gallium arsenide phosphide GaAs.sub.a P.sub.1-a having the predetermined alloy composition a to be grown above the GaP layer; the alloy composition x is abruptly ascended as in composition ascending zones C11 to C13 with the ascended thickness d of an epitaxial layer and then descended as in crystal stabilizing zones S11 to S13 in such a range as not to cancel the previous ascent amount. One or more combinations of such ascent and descent in the alloy composition are repeated to form as distributed in the alloy composition gradient layer 4, and then the alloy composition x is ascended to the predetermined alloy composition a.

Abstract: A structure and the fabrication method of two-color IR detector are disclosed. Disclosed two-color IR detector structure is a n-p-N structure which can be realized using only two-layer HgCdTe. The most important factor in the two-color IR detector structure is the formation of the potential barrier in the conduction band of p-N heterojunction. This potential barrier prevents photogenerated minority carriers in p-HgCdTe region from diffusing to and being collected by N-HgCdTe region (larger band gap diode). The calculated potential barrier heights under the thermal equilibrium at 77 K are 21 kT (141 meV) and 13.4 kT (89 meV) for the cases of p-Hg.sub.0.78 Cd.sub.0.22 Te/N-Hg.sub.0.69 Cd.sub.0.3l Te and p-Hg.sub.0.69 Cd.sub.0.31 Te/N-Hg.sub.0.636 Cd.sub.0.364 Te with each side carrier concentration of 5.times.10.sup.15 and 1.times.10.sub.16 cm.sup.-3, respectively.

Abstract: An integrated circuit which includes a first transistor device portion having an N+ doped region drain terminal in an N- well in a P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; and a second transistor device portion including an N+ doped region drain terminal in the P- substrate, an N+ doped region source terminal in the P- substrate, and a gate separated from the source and drain regions by a layer of silicon dioxide; conductive means connecting the drain region of the first transistor device portion to a node to be discharged, a conductor connecting the gate of the first transistor device portion to a source of biasing potential equal to the source voltage used in a low voltage process, another conductor connecting the source of the second transistor device portion to a source of ground potential; and a third conductor for providing a source of positive input potential to the gate terminal of the se

Abstract: The present invention relates to the fabrication of a boron carbide/boron diode on an aluminum substrate, and a boron carbide/boron junction field effect transistor. Our results suggest that with respect to the approximately 2 eV band gap pure boron material, 0.9 eV band gap boron carbide (B.sub.5 C) acts as a p-type material. Both boron and boron carbide (B.sub.5 C) thin films were fabricated from single source borane cage molecules using plasma enhanced chemical vapor deposition (PECVD). Epitaxial growth does not appear to be a requirement. We have doped boron carbide grown by plasma enhanced chemical vapor deposition. The source gas closo-1,2-dicarbadecaborane (orthocarborane) was used to grow the boron carbide while nickelocene (Ni(C.sub.5 H.sub.5)2) was used to introduce nickel into the growing film. The doping of nickel transformed a B.sub.5 C material p-type relative to lightly doped n-type silicon to an n-type material.

Abstract: A coverage can be improved when an upper layer is formed on an upper wiring patterned on an interlayer insulation film. A sidewall made of an insulating material is bonded to a side face of the upper wiring patterned on the interlayer insulation film. Consequently, a height difference between the upper wiring and the interlayer insulation film has a small gradient. By flattening a laminated face of the upper layers including surfaces of the upper wiring and the sidewall, a further upper layer to be formed can have a coverage improved.

Abstract: An LED chip 41 is mounted in a horizontal state in such a manner that a PN junction surface 42 is in perpendicular to a unit substrate 45. A side surface of a crystal surface of the LED chip 41 is recessed in such a manner as to have a distance with respect to a surface of the unit substrate 45, or is wholly covered by an electrically insulating film 52 formed of an ultraviolet curable type resin, so that even when the LED chip is in contact with wiring patterns 46, 47 of the unit substrate 45, an electric trouble such as an electrical short is not generated. An electrical connection to the LED chip 41 is performed by connecting thick film electrodes 53, 54 provided on both sides in a perpendicular direction to a PN junction surface, and the wiring patterns 46, 47 on the unit substrate 45 to each other through electrically conductive pastes 56, 57.

Abstract: A photodetector design is disclosed for preventing an electrode from being broken. A recess portion is formed in a semiconductor substrate. A light absorbing layer is formed in the recess portion, and a buffer layer is formed on the light absorbing layer. A contact layer is formed on the buffer layer. The height of the light absorbing layer can be set to minimize the effect of a step caused by facet formation. An insulating layer is formed outside of a recess portion to project from a main surface of the substrate. The anode electrode is formed on the insulating layer and substantially outside of the recess and, as a result, the electrode is less likely to be broken.

Abstract: An electronic device includes one or more GaAs integrated circuits having a plurality of mutually independent field-effect transistors formed on a GaAs base-member; and one or more high-dielectric-constant base-members including a passive element on a surface thereof or therein.

Abstract: A detector with quantum structure comprising a small-gap semiconductor material inserted between two large-gap semiconductor materials, the structure comprising a coupling grating between the wave to be detected and the detector zone constituted by the small-gap material. Under these conditions, the detector zone may have a very small thickness (typically of the order of 1,000 .ANG.) and lead to a detectivity, limited by the dark current, that is high.

Abstract: A semiconductor light emitting device includes a substrate and semiconductor overlying layers formed on the substrate. A light emitting layer is formed in the semiconductor layer so as to emit light. The substrate is transmittable of the light emitted by the light emitting layer. A light reflecting layer is formed on a part of a back surface of the substrate. As a result, a semiconductor light emitting device is obtainable by easily dividing a wafer having thereon a light emitting film through recognizing, from a wafer back side, semiconductor layer chip pattern formed overlying the main surface of the wafer.

Abstract: Formed on a grounded semiconductor substrate, via an insulation layer, is a semiconductor layer of the same conductive type as that of the substrate. Formed on the semiconductor layer are source and drain regions of the different conductive type from that of the substrate. The drain region is formed so that its portion reaches the insulation layer. A gate insulation film is formed on the semiconductor layer and a gate electrode is formed on the gate insulation film and between the source and drain regions. A conductive member is embedded in a through hole formed from a portion of the semiconductor layer to the semiconductor substrate via the insulation layer. A source electrode is formed so that the conductive member in the through hole and the source region are connected to each other by means of the source electrode. A drain electrode is connected to the drain region.

Abstract: A method for fabricating a bipolar device, including the steps of forming an epitaxial growth retarding layer on a substrate at a predetermined angle, forming a collector layer on the substrate so that the collector layer is adjacent the epitaxial growth retarding layer and has an inclined portion formed over an edge portion of the epitaxial growth retarding layer, forming a base layer having an inclined portion on the collector layer, and forming an emitter layer on the inclined portion of the base layer.