Abstract: The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latter comprising at least two dielectric layers of which the first dielectric layer covers the isolation layer with its edges as well as the substrate in an outer edge zone of the window, and of which the second dielectric layer covers the first dielectric layer also over the edge of the isolation layer and in a portion of the outer region of the window.

Abstract: In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.

Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.

Abstract: The leakage current at the silicon-to-silicon dioxide interfaces of an active pixel sensor cell is substantially reduced by eliminating field oxide from the cell, and by insuring that, during integration, every surface region of the cell that is not heavily doped is either biased into accumulation or biased into inversion. Each of these states, in turn, substantially limits the number of electrons from thermally-generated electron-hole pairs at the surface that can contribute to the leakage current.

Abstract: An FET isolated on either side by a trench. The FET has a dielectric layer in the isolating trench along at least one side. The dielectric layer which may be an ONO layer has an oxidation catalyst diffused into it. The oxidation catalyst may be potassium. A gate oxide along the side of the FET in close proximity to the ONO layer is thicker than gate oxide between both sides.

Abstract: A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.

Abstract: A semiconductor device which includes a mesa type silicon film with a source/drain region and a channel region formed therein, a gate oxide film formed on the mesa type silicon film, and a gate electrode provided on the mesa type silicon film through the gate oxide film, wherein an oxide film having a thickness greater than that of the gate film is formed at the top edge section of the mesa type silicon which is present under the gate electrode, as well as a method for manufacturing it.

Abstract: A method for improving oxide quality by implanting both nitrogen and fluorine ions into the oxide layer through a polysilicon layer to prevent the penetration of impurities into the oxide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. Fluorine ions are implanted through the polysilicon layer wherein the fluorine ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. Thereafter, nitrogen ions are implanted through the polysilicon layer wherein the nitrogen ions congregate at the interface between the gate silicon oxide layer and the surface of the semiconductor substrate. The substrate is annealed. The polysilicon and gate silicon oxide layers are patterned to form gate electrodes and interconnection lines.