Abstract: A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.

Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe segment and a plastic body. The leadframe segment includes lead fingers attached and wire bonded to the die, and opposing volume equalizing members proximate to lateral edges of the die. The volume equalizing members are downset from a first plane proximate to a face of the die, to a second plane proximate to a center line of the package. In addition, the volume equalizing members are configured to rigidify the package, and to substantially equalize the volumes of molding compound on either side of the package center line and leadframe segment. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained.