Abstract: A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

Abstract: A method includes determining, by a first component of a memory sub-system controller, a first temperature value of the memory subsystem controller. The method can further include determining, by a second component of a non-volatile memory device, a second temperature value of the non-volatile memory device coupled to the memory sub-system controller. The method can further include modifying a data parameter in response to at least one of the first temperature value or the second temperature value exceeding a threshold temperature value.

Abstract: A memory device includes: a memory cell array; a first latch; a second latch; a first circuit; and a second circuit. The memory cell array includes first, second, and third columns associated with first, second, and third addresses, respectively. The first latch stores the first address and is associated with a fourth address. The second latch stores the second address and is associated with a fifth address. The fourth address and the fifth address are in an ascending order. The first circuit selects the third column in place of the first column based on the first address. The second circuit determines whether or not the first address and the second address are in an ascending order.

Abstract: A resistive memory device includes a resistive memory cell, a source line connected to one end of the resistive memory cell, a bit line connected to another end of the resistive memory cell, and a sensing circuit connected to the source line and the bit line. The sensing circuit is configured to generate a pull-up signal that is pulled up from a first voltage level to a second voltage level, based on a read current flowing through the resistive memory cell, generate a pull-down signal that is pulled down from a third voltage level to a fourth voltage level, based on the read current, and determine data that is stored in the resistive memory cell, based on a difference between the generated pull-up signal and the generated pull-down signal.

Abstract: Systems and methods for an optical ternary content addressable memory (TCAM) are provided. The optical TCAM implements a time-division multiplexing (TDM) based encoding scheme to encode each bit position of a search word in the time domain. Each bit position is associated with at least two time slots. The encoded optical signal comprising the search word is routed through one or more modulators configured to represent a respective TCAM stored word. If a mismatch between at least one bit position of the search word and at least one TCAM stored word occurs, a photodetector or photodetector array will detect light.

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

Abstract: A memory comprising: a resistive-switching element having first and second electrodes separated by a layer of insulator; an energy storage component or load coupled to the resistive-switching element via a first switch; and a control circuit configured: to program the resistive-switching element to have a set state, wherein, in the set state, a filament forms a conducting path between the first and second electrodes; and, following a dissolution of the filament, to recover electrical energy, generated by the dissolution of the filament, from one of the first and second electrodes by activating the first switch.

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract: Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Abstract: A memory device includes a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N/2+1) bit lines, (N/2) source lines and reference cells, N being a positive even integer. Each row of reference cells includes a (2n?1)th reference cell and a (2n)th reference cell. The (2n?1)th reference cell includes a first terminal coupled to an nth bit line, and a second terminal coupled to an nth source line, n being a positive integer less than N/2+1. The (2n)th reference cell includes a first terminal coupled to an (n+1)th bit line, and a second terminal coupled to the nth source line. The detection circuit compares a data current outputted from the data memory array and a reference current outputted from the reference memory array to determine a data state of a memory cell.

Abstract: A memory includes read circuitry for reading values stored in memory cells. The read circuitry includes flipped voltage followers for providing bias voltages to nodes of current paths coupled to sense amplifiers during memory read operations.

Abstract: A memory device may include a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform a program verify operation for a target program state among a plurality of program states on selected memory cells among the plurality of memory cells. The control logic is configured to control the peripheral circuit to precharge bit lines coupled to first memory cells among the selected memory cells and bit lines coupled to second memory cells among the selected memory cells in the program verify operation. The first memory cells are program-passed memory cells among memory cells programmed to a program state higher than the target program state among the plurality of program states. The second memory cells are memory cells programmed to a program state lower than or equal to the target program state among the plurality of program states.

Abstract: An analog content addressable memory (aCAM) that enables parallel searching of analog ranges of values and generates analog outputs that quantify matches between input data and stored data is disclosed. The input data can be compared with the stored data, and the input data can be determined to match the stored data based on a value associated with the input data being within a range associated with the stored data. The aCAM can generate an analog output that represents a number of matches and a number of mismatches between the input data and the stored data. Based on the analog output, whether the input data matches the stored data and a degree to which the input data matches the stored data can be determined.

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

Abstract: Apparatus having a controller configured to connect a string of series-connected memory cells (e.g., a NAND string) to a node, perform a sensing operation on a selected memory cell of the NAND string while the selected memory cell is connected to the node through a first field-effect transistor (FET) between the node and the NAND string and through a second FET between the first FET and the NAND string, connect a control gate of the first FET to receive a lower voltage level after performing the sensing operation, connect the control gate of the second FET to receive the lower voltage level after connecting the control gate of the first FET to receive the lower voltage level, and connect a control gate of the selected memory cell to receive the lower voltage level after connecting the control gate of the second FET to receive the lower voltage level.

Abstract: According to one embodiment, a memory system includes a memory controller and a nonvolatile memory with multiple planes each provided with multiple word lines, memory cell groups, dummy word lines, and dummy memory cell groups. The memory controller writes data to a memory cell group connected to a corresponding word line of any of the planes, such that a plane to which k-th data are to be written is different from a plane to which (k+m?1)-th data are to be written, and writes the parities to any of the dummy memory cell groups. The combinations of the data used for generating the different parities are different from each other.

Abstract: A circuit for performing energy-efficient and high-throughput multiply-accumulate (MAC) arithmetic dot-product operations and convolution computations includes a two dimensional crossbar array comprising a plurality of row inputs and at least one column having a plurality of column circuits, wherein each column circuit is coupled to a respective row input. Each respective column circuit includes an excitatory memristor neuron circuit having an input coupled to a respective row input, a first synapse circuit coupled to an output of the excitatory memristor neuron circuit, the first synapse circuit having a first output, an inhibitory memristor neuron circuit having an input coupled to the respective row input, and a second synapse circuit coupled to an output of the inhibitory memristor neuron circuit, the second synapse circuit having a second output. An output memristor neuron circuit is coupled to the first output and second output of each column circuit and has an output.

Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.

Abstract: Embodiments of a memory, and calibration and operation methods thereof for reading data in memory cells are disclosed. In an example, first data from a plurality of memory cells is sensed, each of the first data corresponding to a first bit. Measurements of first currents converted from voltages of the first data are obtained. Second data from the plurality of memory cells is sensed, each of the second data corresponding to a second bit which is different from the first bit. Measurements of second currents converted from voltages of the second data are obtained. One or more parameters corresponding to one or more components of a charge sharing circuit are adjusted until each of a plurality of reference currents provided by a plurality of transistors is within a predetermined range of a nominal value determined based on the measurements of first currents and the measurements of second currents.

Abstract: A semiconductor device includes a data input/output control block including a first power gating circuit coupled to a supply terminal of a first voltage and a second power gating circuit coupled to a supply terminal of a second voltage, the data input/output control block suitable for generating a control signal using the first and second voltages, a data input/output block including a third power gating circuit coupled to any one of the supply terminal of the first voltage and the supply terminal of the second voltage, the data input/output block suitable for inputting and outputting a data signal using the first and second voltages based on the control signal, and a memory block, coupled to the data input/output block, suitable for writing or reading the data signal.