Abstract: A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.

Abstract: A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.

Abstract: A hybrid modulator apparatus includes a modulator that amplitude modulates a power supply signal. A correction circuit coupled in parallel with the modulator reduces errors caused by the modulator. In one embodiment the modulator includes a digital pulse-width modulator (PWM) and a buck converter. The K most significant bits (MSBs) of N-bit input digital words are used by the digital PWM and a buck converter to generate an amplitude modulated power supply signal having a plurality of quantized voltage levels. The remaining N?K bits of each N-bit words may be used to dither the input drive to the PMW, to produce an error signal at the output of the modulator representing quantization errors caused by only applying the K MSBs to the PWM. The correction circuit compares the error signal to a signal formed form all N bits of the N-bit words in reducing the quantization errors.

Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

Abstract: A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract: An oscillating circuit includes a charge pump, a loop filter and a voltage controlled oscillator. The charge pump and the loop filter generates a differential voltage signal. The loop filter is responsive to the differential voltage signal and generates a filtered differential voltage control signal that is proportional to the differential voltage signal. The voltage controlled oscillator is responsive to the filtered differential voltage control signal and generates a periodic signal that has a frequency that corresponds to the filtered differential voltage control signal.

Abstract: An oscillator coupling system includes a plurality of oscillating members and a plurality of delay members connecting at least two of the oscillating members. Between the delay members is a specific phase or time delay relationship such that characteristics of phase or frequency noise suppression correlation of the two oscillating members are coupled to each other by the delay members, thereby reducing noise autocorrelation while the oscillator coupling system is in operation, enhancing phase or frequency noise suppression, using no bulky elements such as solid state circulators, isolators and resonators, reducing signal distortion, and increasing system stability.

Abstract: Disclosed herein is a sine wave oscillator having a self-startup circuit. The sine wave oscillator can start up and output sine waves having a constant frequency without receiving any signals other than supply voltage. The sine wave oscillator includes an operational amplification unit, a first resistor, a first capacitor, a second capacitor, a second resistor, a third resistor, a fourth resistor, and a startup circuit.

Abstract: A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

Abstract: A harmonic-rejection modulation device is provided, which includes a phase splitter, a low pass filter, and a modulator. Based on a square wave, the phase splitter generates a plurality of unfiltered local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The low pass filter filters the high frequency components of the unfiltered local oscillating signals to generate a plurality of local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The modulator modulates a baseband signal with the local oscillating signals, wherein the third harmonics of the local oscillating signals are eliminated by the modulation process of the modulator. The invention also provides a method of modulating a baseband signal.

Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A phase locked loop with phase clipping and/or resynchronization is disclosed. A reference signal is compared to a feedback signal derived at least in part from an output signal of an oscillator to determine a phase error. A magnitude of at least one of the phase error and a change in the phase error, if required, is clipped to provide at least one of a clipped phase error that has a clipped magnitude that does not exceed a prescribed maximum phase error and a clipped change in phase error that has a clipped magnitude that does not exceed a prescribed maximum change in phase error. If a resynchronization triggering event is detected, the oscillator is resynchronized with the reference signal.

Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

Abstract: A circuit has a first capacitive circuit component, having a first terminal and a second terminal, and an amplifier, having a first input and an output, the first input coupled to the first terminal and the output coupled to the second terminal to generate a potential difference between the first terminal and the second terminal.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: A novel gear shifting mechanism operative to adjust the loop gain of a phase locked loop (PLL) circuit in a continuous and reversible manner. The loop gain can be increased to widen the bandwidth of the loop and can also be decreased to narrow the loop bandwidth. The mechanism incorporates an ? gear shift circuit, a ? gear shift circuit and an optional IIR gear shift circuit. The ? gear shift circuit comprises a infinite impulse response (IIR) filtering which enables hitless operation of the PLL loop at the occurrence of gear shift events. The ? gear shift circuit comprises an accumulator whose output is multiplied by the gain value ?. The invention enables multiple gear shifts in either positive or negative direction to be achieved by configuring the loop gain variables ? and ? which may be accomplished in software.

Abstract: To calibrate an oscillator for microcontroller chip operation, an RC circuit is coupled to the microcontroller circuitry and a voltage signal is applied to the capacitor for changing the voltage across the capacitor. The voltage value across the capacitor is measured and compared to an expected voltage value. Adjustments to the frequency of the clock signal generated by the oscillator are made in response to the comparison.

Abstract: An oscillator starting control circuit capable of shortening a starting time and stably controlling the starting time, and furthermore, stabilizing an oscillating frequency after starting an oscillating circuit. An oscillating circuit (1) is a crystal oscillating circuit in which an input and an output of an inverter (14) are connected to both ends of a crystal oscillator (15) and both ends of a resistor (16), the input is connected to a drain of an MOS variable capacity (10), the output is connected to a drain of an MOS variable capacity (11), a source of the MOS variable capacity (10) is connected to a fixed capacity (12), a source of the MOS variable capacity (11) is connected to a fixed capacity (13), and the other ends of the fixed capacities (12, 13) are connected to a GND.