Abstract: A semiconductor device is disclosed. One embodiment provides a cell area and a junction termination area at a first side of a semiconductor zone of a first conductivity type. At least one first region of a second conductivity type is formed at a second side of the semiconductor zone. The at least one first region is opposed to the cell area region. At least one second region of the second conductivity type is formed at the second side of the semiconductor zone. The at least one second region is opposed to the cell area region and has a lateral dimension smaller than the at least first region.

Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a plurality of pixels, wherein each pixel includes a scan line extending in a first direction. Each pixel also includes a data line extending in a second direction crossing the first direction and a driving thin-film transistor (TFT) formed adjacent to the data line and including a gate electrode, a source electrode, and a drain electrode. The pixel also includes an interlayer insulating layer formed between the data line and the driving TFT, and a first through hole is formed in the interlayer insulating layer to be adjacent to the data line and the gate electrode. Each pixel also includes a driving voltage line formed adjacent to the data line and including a first portion formed in the first through hole and formed on the interlayer insulating layer.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.

Abstract: A method of inspecting and forming sapphire structures. The method of inspecting a sapphire structure may include providing an annealed sapphire structure, and measuring a profile of at least a portion of the annealed sapphire structure. The profile of at least the portion of the annealed sapphire structure may be measured using a non-x-ray based measuring device. Additionally, the method of inspecting may include identifying a defect within at least a portion of the measured profile of the annealed sapphire structure.

Abstract: A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

Abstract: A light-emitting device includes a support including a substrate, a pair of electrodes and an insulating reflective member, the pair of electrodes being disposed on an upper surface of the substrate, and the reflective member being disposed on the substrate, a light-emitting element flip-chip mounted on the pair of electrodes, and a resin member disposed at least between the light-emitting element and the reflective member, the resin member including a conductive substance which electrically connects the light-emitting element to the pair of electrodes, the reflective member being disposed at least over an entirety of a surface that is located immediately below the resin member.

Abstract: A junctionless light emitting device comprises a field emitter cathode, and a light emitting semiconductor material sandwiched between an ohmic contact (OC) that faces the injected electrons and a Schottky contact (SC). The field emitter cathode is configured to inject electrons into the ohmic contact.

Abstract: An organic light emitting diode display and a manufacturing method thereof are provided. The organic light emitting diode display includes a first substrate, a second substrate, a plurality of organic light emitting diodes, and a frit layer. The organic light emitting diodes are disposed on the first substrate, and the frit layer adheres the first substrate and the second substrate to each other. The frit layer includes a first porous region having pores, a second porous region having pores, and a third porous region having pores. The number of the pores of the first porous region with a diameter of larger than or equal to 4 ?m and smaller than or equal to 15 ?m is greater than the number of the pores of the second porous region with the above-mentioned diameter range.

Abstract: Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Abstract: A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening.

Abstract: Stable electrical characteristics of a transistor including an oxide semiconductor layer are achieved. A highly reliable semiconductor device including the transistor is provided. The semiconductor device includes a multilayer film formed of an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the oxide layer, and a gate electrode overlapping with the multilayer film with the gate insulating film interposed therebetween. The oxide layer contains a common element to the oxide semiconductor layer and has a large energy gap than the oxide semiconductor layer. The composition between the oxide layer and the oxide semiconductor layer gradually changes.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap.

Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd).

Abstract: A microelectronic socket having a two piece construction, wherein a first piece comprises a conductive socket substrate and the second piece comprises an insulative insert. The conductive socket substrate has a first surface, a second surface, and at least one opening extending therebetween. The insulative insert has a base portion with at least one projection extending therefrom. The insulative insert is mated with the conductive socket substrate such that the at least one projection resides within a corresponding conductive socket substrate opening. The insulative insert further includes a plurality of vias, wherein at least one of the plurality of vias extends through the insulative base and through an insulative insert projection, wherein a contact may be disposed within the via.

Abstract: A method of forming a semiconductor structure includes depositing a high-k dielectric layer within a first recess located between sidewall spacers of a first CMOS device and within a second recess located between sidewall spacers of a second CMOS device. A dummy titanium nitride layer is deposited on the high-k dielectric layer. Next, the high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess in the second CMOS device. A silicon cap layer is deposited within the first recess and the second recess, the silicon cap layer is located above the high-k dielectric layer and dummy titanium nitride layer in the first CMOS device. Subsequently, dopants are implanted into the silicon cap layer located in the second recess of the second CMOS device.

Abstract: A transparent conductive layer structure for an LED is provided. The LED includes a reflecting layer, an N-type electrode, an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, a current block layer, a transparent conductive layer and a P-type electrode that are stacked on a substrate. The current block layer is disposed between and separates the P-type electrode and the P-type semiconductor layer. The transparent conductive layer is disposed between the P-type electrode and the current block layer, and connects to the P-type electrode and the P-type semiconductor layer. At a region corresponding to the P-type electrode, a plurality of holes are disposed at the transparent conductive layer to reduce an area of and hence an amount of light absorbed by the transparent conductive layer, thereby increasing light extraction efficiency of excited light from the light emitting layer and enhancing light emitting efficiency of the LED.

Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.