Patents Examined by J. V. Clark
  • Patent number: 5910687
    Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: June 8, 1999
    Assignee: ChipScale, Inc.
    Inventors: Changsheng Chen, Phil P. Marcoux, Wendell B. Sander, James L. Young