Patents Examined by Jacinta M Crawford
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Patent number: 11727526Abstract: Disclosed herein are systems and methods for detecting when geometry shaders output a constant amount of data and writing the data into an output stream buffer. In one aspect, an exemplary method comprises gathering information about a number of block executions associated with the received data, analyzing the gathered information to determine whether constant or variable amount of data is generated for at least one of: a stream output or a rasterization, and when the constant amount of data is generated for the stream output, writing the generated data directly into a stream output buffer, and when the constant amount of data is generated for the rasterization, writing the generated data into a rasterization buffer either directly or through a use of an intermediate index buffer.Type: GrantFiled: September 23, 2021Date of Patent: August 15, 2023Assignee: Parallels International GmbHInventors: Evgeny Nikitenko, Alexey Ivanov, Nikolay Dobrovolskiy
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Patent number: 11727525Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: GrantFiled: May 28, 2021Date of Patent: August 15, 2023Assignee: Imagination Technologies LimitedInventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Patent number: 11715252Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.Type: GrantFiled: February 4, 2021Date of Patent: August 1, 2023Inventors: Keshavan Varadarajan, David C. Tannenbaum, F N U Gurupad
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Patent number: 11715175Abstract: Tiling engines and methods for hierarchically tiling a plurality of primitives. A chain of sorting units includes a top level sorting unit followed by lower level sorting units, the top level sorting unit determining which of a plurality of regions of a render space each of the plurality of primitives at least partially falls within. For each region a primitive at least partially falls within an identifier of that primitive is stored in a queue. Each of the lower level sorting units selects queues of a preceding sorting unit in the chain to process, and determines which of a plurality of sub-regions of the region associated with that queue each of the primitives at least partially falls within. For each such sub-region an identifier of that primitive is stored in a queue of the lower level sorting unit that is associated with that sub-region. An output unit outputs the primitives identified in the queues of the last lower level sorting unit in the chain on a queue by queue basis.Type: GrantFiled: October 19, 2021Date of Patent: August 1, 2023Assignee: Imagination Technologies LimitedInventors: Robert Brigg, Lorenzo Belli
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Patent number: 11710207Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.Type: GrantFiled: March 30, 2021Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Christopher J. Brennan, Nishank Pathak
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Patent number: 11703334Abstract: An example robot performs a scan to obtain image data of a given region. The robot performs image analysis on the image data to detect a set of undesirable objects, and generates a reference map that excludes the set of undesirable objects, where the reference map is associated with the location of the robot at the time of the scan.Type: GrantFiled: October 31, 2017Date of Patent: July 18, 2023Assignee: Hewlett-Packard Development Company. L.P.Inventors: Jonathan Salfity, David Murphy
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Patent number: 11704546Abstract: An apparatus for, by inputting data to a hierarchical neural network and performing operation processing in each layer of the network, calculating a feature plane in the layer, comprises an operation unit, a feature plane holding unit including at least one memory that holds a feature plane to be processed, a unit configured to control to arrange the feature plane in the memory based on network information as information about each layer undergoing the operation processing and to manage reading/writing from/in the memory, and a processor configured to access, via a bus, the feature plane holding unit which is address-mapped in a memory space. The processor calculates, based on the network information, an address address-mapped in the memory space, reads out the feature plane, and processes the feature plane.Type: GrantFiled: June 30, 2020Date of Patent: July 18, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Shiori Wakino
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Patent number: 11699304Abstract: An imaging device includes: an imaging portion that captures an image of a portion of a living body to take in the image; a display portion that displays first and second display images with being superimposed on each other, the first display image being based on the taken-in image, the second display image including guidance regarding a way to place the portion of the living body in a prescribed position; a determination portion that determines whether the portion of the living body is placed in the prescribed position; and a control portion that, until it is determined that the portion of the living body is placed in the prescribed position, causes the imaging portion to newly capture and take in a new image of the portion of the living body and causes the display portion to display an image based on the new taken-in image.Type: GrantFiled: November 18, 2019Date of Patent: July 11, 2023Assignee: NEC CORPORATIONInventors: Takahiro Sakamoto, Masaki Kuroiwa
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Patent number: 11694371Abstract: An apparatus, method, and computer readable medium that access a frame buffer of a graphics processing unit (GPU), analyze, in the frame buffer, a frame representing displayed data, based on the analyzed frame, identify a reference patch that includes an instruction to retrieve content, generate an overlay including an augmentation layer which includes the content, superimpose the overlay onto the displayed data such that the content is viewable while a portion of the base layer is obscured, detect a user input, determine a location of the user input in the augmentation layer, associate the location in the augmentation layer with a target location in the base layer, and associate, within memory, the target location with an operation such that the user input in the augmentation layer activates an input in the base layer.Type: GrantFiled: September 2, 2022Date of Patent: July 4, 2023Assignee: MOBEUS INDUSTRIES, INC.Inventors: Dharmendra Etwaru, Michael R. Sutcliff, Aram Andriasyan
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Patent number: 11694398Abstract: Disclosed is a system that receives a point cloud, and that generates a Bounding Volume Hierarchy (“BVH”) based on the point cloud data points. The BVH includes leaf nodes and parent nodes at one or more levels above the leaf nodes. The leaf nodes correspond to the point cloud data points. The system may receive input for adjusting a first set of elements of data points that are identified based on values specified for a second set of elements, and may locate those data points by traversing the BVH to arrive at a particular parent node that encompasses the values specified for the second set of elements. The system may then modify, based on the input, the first set of elements of a set of data points that correspond to a set of leaf nodes from the BVH that are directly or indirectly linked to the particular parent node.Type: GrantFiled: September 8, 2022Date of Patent: July 4, 2023Assignee: Illuscio, Inc.Inventor: Robert Monaghan
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Patent number: 11694377Abstract: An editing device acquires a first image in which an occupant of a vehicle has been imaged in association with a time point in a time series and a second image in which scenery around the vehicle has been imaged in association with a time point in a time series, acquires first index information indicating feelings of the occupant when the first image has been captured on the basis of the first image, and extracts the first image and the second image from first images of the time series and second images of the time series on the basis of the first index information and the time point associated with the first image based on the first index information to generate a library including the extracted images.Type: GrantFiled: August 3, 2021Date of Patent: July 4, 2023Assignee: HONDA MOTOR CO., LTD.Inventors: Yuki Aoki, Hisashi Murayama, Koichi Kono, Masahide Kobayashi
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Patent number: 11694651Abstract: Technology for a display source controller is described. The display source controller can receive display pixel data from a display source. The display source controller can convert the display pixel data to display symbol data that includes a plurality of 32-bit double words (DWords). The display source controller can divide the display symbol data that includes the plurality of 32-bit DWords for a number of unidirectional serial data channels. The display source controller can process, for each unidirectional serial data channel, the display symbol data at a 32-bit DWord granularity level. The display source controller can send the display symbol data for each of the unidirectional serial data channels over a physical serial link to a display panel.Type: GrantFiled: February 28, 2022Date of Patent: July 4, 2023Assignee: Intel CorporationInventor: Nausheen Ansari
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Patent number: 11694384Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.Type: GrantFiled: October 30, 2020Date of Patent: July 4, 2023Assignee: QUALCOMM IncorporatedInventors: Thomas Edwin Frisinger, Richard Hammerstone, Andrew Evan Gruber, Gang Zhong, Yun Du, Jonnala Gadda Nagendra Kumar
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Patent number: 11688124Abstract: A background image is also generated, e.g., by filling portions of a captured image where a foreground object was extracted and communicated to the playback device, Foreground objects are identified and point cloud representations of the foreground objects are generated and communicated to a playback device so that they can be used in generating images including the background which is communicated separately. In the case of a point cloud representation a number of points in an environment, e.g., 3D space, are communicated to the playback device along with color information. Thus in some embodiments a foreground object is represented as a set of points with corresponding color information on a per point basis. Foreground object information is communicated and processed in some embodiments at a different rate, e.g., faster rate, then the background textures. The playback device renders images which are sent to the display by first rendering a background layer using the communicated background information, e.g.Type: GrantFiled: February 14, 2022Date of Patent: June 27, 2023Assignee: Nevermind Capital LLCInventors: Hector Medina, David Cole, Alan Moss
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Patent number: 11682102Abstract: Disclosed herein are system, method, and computer program product embodiments for modifying graphics rendering by transcoding a serialized command stream. An embodiment operates by receiving a command configured to instruct an API to render a graphics element. The embodiment further operates by generating, based on the command, a transcoded command configured to instruct the API to render a modified graphics element by applying a set of modification factors to a portion of the command. Subsequently, the embodiment operates by transmitting the transcoded command to the API.Type: GrantFiled: May 26, 2022Date of Patent: June 20, 2023Assignee: ROKU, INC.Inventor: Matthew James Sottek
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Patent number: 11682100Abstract: In various examples, a signal processing pipeline is dynamically generated or instantiated for a signal processing request. To generate the pipeline, a graph topology—including nodes and edges—may be created to represent features, functionality, and characteristics of a signal processing system. The nodes, representing processing tasks, may be connected via edges having associated costs for performing, by a node, a processing task on an output of a prior or edge-connected node. For a given signal processing request, the nodes or processing tasks to be included may be selected and, using a graph routing algorithm and the costs between and among the determined nodes, a path through the nodes may be determined—thereby defining, at least in part, the signal processing pipeline.Type: GrantFiled: March 29, 2022Date of Patent: June 20, 2023Assignee: NVIDIA CorporationInventors: David Schalig, Karsten Patzwaldt
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Patent number: 11676325Abstract: A method of generating an intermediate layer comprises generating local surface properties for a graphics object from parameter image maps, generating a first object image surface layer based on the local surface properties, storing intermediate surface results as an object image layer from the object local surface properties, and rendering a second object image surface layer based on the stored intermediate surface results.Type: GrantFiled: May 3, 2021Date of Patent: June 13, 2023Assignee: Oxide Interactive, Inc.Inventors: Timothy James Kipp, Daniel Kurt Baker
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Patent number: 11669249Abstract: A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.Type: GrantFiled: June 24, 2020Date of Patent: June 6, 2023Assignee: SK hynix Inc.Inventor: Young Jae Jin
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Patent number: 11669329Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.Type: GrantFiled: April 18, 2022Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg, Chandra S. Gurram, Junjie Gu, Guei-Yuan Lueh, Subramaniam Maiyuran, Jorge E. Parra, Sudarshan Srinivasan, Varghese George
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Patent number: 11669366Abstract: Methods, systems, and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.Type: GrantFiled: July 16, 2022Date of Patent: June 6, 2023Assignee: Blaize, Inc.Inventors: Lokesh Agarwal, Sarvendra Govindammagari, Venkata Ganapathi Puppala, Satyaki Koneru