Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations.

Abstract: One embodiment provides for a graphics processing unit to perform computations associated with a neural network, the graphics processing unit comprising compute unit including a hardware logic unit having dynamic precision fixed-point logic, the compute unit to receive a set of dynamic fixed-point tensors, compute, via the dynamic precision fixed-point logic, a right-shift value using an absolute maximum value within the set of dynamic fixed-point tensors and a dynamic range of the set of dynamic fixed-point tensors, right-shift data values within the set of dynamic fixed-point tensors based on the right-shift value, increment a shared exponent associated with the set of dynamic fixed-point tensors based on the right-shift value, perform a compute operation on the set of dynamic fixed-point tensors, and generate an output tensor via the compute operation on the set of dynamic fixed-point tensors.

Abstract: In various examples, a signal processing pipeline is dynamically generated or instantiated for a signal processing request. To generate the pipeline, a graph topology—including nodes and edges—may be created to represent features, functionality, and characteristics of a signal processing system. The nodes, representing processing tasks, may be connected via edges having associated costs for performing, by a node, a processing task on an output of a prior or edge-connected node. For a given signal processing request, the nodes or processing tasks to be included may be selected and, using a graph routing algorithm and the costs between and among the determined nodes, a path through the nodes may be determined—thereby defining, at least in part, the signal processing pipeline.

Abstract: A system and a method are disclosed that reduce primitive overdraw in a GPU. An occlusion index (OI) for a first tile of a batch of graphical data. In one embodiment, the first tile is bypassed from an early coverage discard (ECD) first-in, first-out (FIFO) if the OI for the first tile is less than a first threshold, otherwise the first tile is entered into the ECD FIFO. The first tile is also bypassed from the ECD FIFO if the OI for the first tile is greater than a second threshold that is greater than the first threshold. In another embodiment, a queue length is logically changed for the first tile in the ECD FIFO if the OI for the first tile is greater than the first threshold and less than or equal to a third threshold that is greater than the first threshold and less than the second threshold.

Abstract: An image processing apparatus for executing partial processes on each of plural image-section data items, corresponding to plural image sections obtained by dividing an input image into partial regions, in each object of an object group in which plural objects for executing image processing is connected in a directed acyclic graph form, the image processing apparatus includes a processor configured to: assign dependency relationships to the partial processes between the objects; assign a priority to a partial process of an object arranged in a terminal stage of the object group; assign, as a priority of a partial process of an object arranged at a pre-stage side which has at least one partial process that is connected at a post-stage side and that has the dependency relationship assigned, a largest value of the priority; and execute a partial process having become executable according to the dependency relationship, according to the priority.

Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.

Abstract: Various implementations disclosed herein render virtual content with noise that is similar to or that otherwise better matches the noise found in the images with which the virtual content is combined. Some implementations involve identifying noise data for an image, creating a parameterized noise model based on the noise data, generating a noise pattern approximating noise of the image or another image using the parameterized noise model, and rendering content that includes the image and virtual content with noise added based on the noise pattern.

Abstract: An electronic chip, a chip assembly, a computing device, and a method are described. The electronic chip comprises a plurality of processing cores and at least one hardware interface coupled to at least one of the one or more processing cores. At least one processing core implements a game engine and/or a simulation engine and one or more processing cores implements an artificial intelligence engine, whereby implementations are on-chip implementations in hardware by dedicated electronic circuitry. The one or more game and/or simulation engines perform tasks on sensory data, generating data sets that are processed through machine learning algorithms by the hardwired artificial intelligence engine. The data sets processed by the hardwired artificial intelligence engine include at least contextual data and target data, wherein combining both data and processing by dedicated hardware results in enhanced machine learning processing.

Abstract: Disclosed is a system for efficiently accessing a point cloud via a multi-tree deconstruction of the point cloud. The system may receive the point cloud, may differentiate different sets of data points from the point cloud using differentiation criteria, and may generate different trees with each tree having leaf nodes corresponding to one of the differentiated sets of data points and parent nodes defined according to commonality in values of two or more leaf nodes. The system may receive a request to render the 3D environment, load a first tree into memory, generate a first image from the first tree data points, flush the first tree from the memory, load a second tree into the memory, generate a second image from the second tree data points, and present a composite image by combining at least the first image with the second image.

Abstract: There is disclosed a method of processing an input set of indices that may contain one or more primitive restarts to determine which indices correspond to complete primitives. A modified version of the set of indices can then be written out that contains complete primitives. In particular this is done by determining, for each index in the set of indices, the index position of the start of a sequence of indices for a sequence of primitives that the index is part of, and then determined from this whether or not the index position corresponds to the start of a complete primitive.

Abstract: A server that includes a graphics processing unit (GPU) may receive, from a first application that is remote from the server, a first request to reserve a first number of cores of the GPU for a first amount of time. The server may also receive, from a second application that is also remote from the server, a second request to reserve a second number of cores of the GPU for a second amount of time that at least partly overlaps the first amount of time. The server may determine that the first request is associated with a higher priority than the second request and, in response, may reserve the first number of cores for the first amount of time for the first application. The server may send, to the first application, an indication that the first number of cores have been reserved as requested by the first application.

Abstract: An image display system, including: a server and a client terminal, wherein the server includes a server-side hardware processor which performs rendering to generate an initial display image, transmits the initial display image and the image data to the client terminal, at least when rendering is performed to a plurality of pieces of image data, the server executes rendering and transmission of image data so that at least parts of execution periods overlap, the server-side hardware processor executes rendering until end of the transmission, the client terminal is a zero client terminal and includes a client-side hardware processor which displays the received initial display image, and performs rendering of the received image data to generate and display a client display image, and the client terminal executes rendering by switching from the server-side hardware processor to the client-side hardware processor based on end of the transmission.

Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.

Abstract: Technology for a display source controller is described. The display source controller can receive display pixel data from a display source. The display source controller can convert the display pixel data to display symbol data that includes a plurality of 32-bit double words (DWords). The display source controller can divide the display symbol data that includes the plurality of 32-bit DWords for a number of unidirectional serial data channels. The display source controller can process, for each unidirectional serial data channel, the display symbol data at a 32-bit DWord granularity level. The display source controller can send the display symbol data for each of the unidirectional serial data channels over a physical serial link to a display panel.

Abstract: Memories and methods for storing untransformed primitive blocks of variable size in a memory structure of a graphics processing system, the untransformed primitive blocks having been generated by geometry processing logic of the graphics processing system. The method includes: storing an untransformed primitive block in the memory structure, and increasing, by a predetermined amount, a current total amount of memory allocated for storing untransformed primitive blocks; determining an unused amount of the current total amount of memory allocated for storing untransformed primitive blocks; receiving a new untransformed primitive block for storing in the memory structure, and determining whether a size of the new untransformed primitive block is less than or equal to the unused amount; and if it is determined that the size of the new untransformed primitive block is less than or equal to the unused amount, storing the new untransformed primitive block in the memory structure.

Abstract: An image processing device includes an application execution unit which executes an image processing application, an image processing circuit which performs image processing, a memory control circuit which is capable of accessing a plurality of memories and a memory allocation determination unit which determines a memory allocation of the image data on the basis of memory address management information, operation unit-specific information and application information. The application execution unit distributedly stores the image data in the plurality of memories on the basis of the memory allocation determined by the memory allocation determination unit.

Abstract: Disclosed is a system for efficiently accessing a point cloud via a multi-tree deconstruction of the point cloud. The system may receive the point cloud, may differentiate different sets of data points from the point cloud using differentiation criteria, and may generate different trees with each tree having leaf nodes corresponding to one of the differentiated sets of data points and parent nodes defined according to commonality in values of two or more leaf nodes. The system may receive a request to render the 3D environment, load a first tree into memory, generate a first image from the first tree data points, flush the first tree from the memory, load a second tree into the memory, generate a second image from the second tree data points, and present a composite image by combining at least the first image with the second image.

Abstract: Techniques that facilitate matrix factorization associated with graphics processing units are provided. In one example, a computer-implemented method is provided. The computer-implemented method can comprise loading, by a graphics processing unit operatively coupled to a processor, item features from a data matrix into a shared memory. The data matrix can be a matrix based on one or more user features and item features. The computer-implemented method can further comprise tiling and aggregating, by the graphics processing unit, outer products of the data matrix tiles to generate an aggregate value and approximating, by the graphics processing unit, an update to a user feature of the data matrix based on the aggregate value and the loaded item features.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.