Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: This application provides a battery protection circuit, a battery protection board, a battery, and a terminal device. The battery protection circuit includes: a first detection unit; a second detection unit; and a current detection element, a first switch unit, and a second switch unit that are configured to connect to an electrochemical cell in series, to form a charging loop or a discharging loop. The first detection unit corresponds to the first switch unit, and the second detection unit corresponds to the second switch unit. Each detection unit controls, based on a detected voltage at two ends of the same current detection element, a corresponding switch unit to be closed or opened, so as to control the loop to be closed or opened.

Abstract: A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.

Abstract: A method for dynamically generating or interacting with an electromagnetic field includes providing a spatial array of conductive segments, a switching device operable on each of the conductive segments to either allow or block transmission of an electrical signal and a control device operable on the switching device. A sequence of the conductive segments are connected to form a conductive path where each segments intersects with at least two different ones of the conductive segments at a node. The switching device operates to connect a selected first one of the conductive segments with a selected second one of the conductive segments to form the sequence according to a logic signal from the control device. Power is supplied to the conductive path to produce an electromagnetic field which depends at least in part on the spatial arrangement of the connected sequence of the conductive segments.

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

Abstract: A computer design verification system comprising a parsing module configured to receive output messages from a computer design testing tool and to compose from the output messages formatted objects comprising a set of fields having field descriptors and test values; a signoff module holding a plurality of signoff objects, each comprising a plurality of fields having a field descriptor, at least some fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object. The signoff module is configured compare at least one test value in the formatted objects received from the parsing module with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case of a match, associating the severity level of the signoff object with the formatted object.

Abstract: The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal.

Abstract: Various embodiments include modeling a component fault tree for a circuit with an input-side and an output-side component. These include using a fault tree corresponding to a hazard for each respective component, obtaining information about the components of the circuit and a connection between components, and connecting the respective fault trees based on the circuit description. Each fault tree includes an input fault mode or a basic event and an output fault mode. The output fault mode and the input fault mode are each assigned to a component terminal. An output fault mode of the input-side component tree is connected to an input fault mode of the output-side component tree if: there is a connection between the assigned terminal of the input-side component and the output-side component and the output fault mode of the input-side component correlates to an input fault mode of the output-side component.

Abstract: Methods and systems for verifying a property of an integrated circuit hardware design. The method includes formally verifying, using a formal verification tool, that the property is true for the hardware design under a constraint that an instantiation of the hardware design transitions to a quiescent state at a symbolic time.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems and methods for generating defect criticality are disclosed. Such systems and methods may include identifying defect results including a defect and a defect location. Such systems and methods may include receiving fault test recipes configured to test potential faults at a plurality of testing locations. Such systems and methods may include identifying a plurality of N-detect parameters based on a countable number of times the fault test recipes are configured to test a potential fault. Such systems and methods may include determining a plurality of weighting parameters based on the plurality of N-detect parameters. Such systems and methods may include generating the defect criticality for the defect based on a proximity between the plurality of testing locations and the defect location and the plurality of weighting.

Abstract: Hybrid quantum-classical approaches for solving computational problems in which results from a quantum processor are combined with an exact method executed on a classical processor are described. Quantum processors can generate candidate solutions to a combinatorial optimization problem, but since quantum processors can be probabilistic, they are unable to certify that a solution is an optimal solution. A hybrid quantum-classical exact solver addresses this problem by combining outputs from a quantum annealing processor with a classical exact algorithm that is modified to exploit properties of the quantum computation. The exact method executed on a classical processor can be a Branch and Bound algorithm. A Branch and Bound algorithm can be modified to exploit properties of quantum computation including a) the sampling of multiple low-energy solutions by a quantum processor, and b) the embedding of solutions in a regular structure such as a native hardware graph of a quantum processor.

Abstract: This disclosure describes a quantum noise process analysis method, device, and storage medium, in the field of quantum processing technologies. The method may include performing quantum process tomography (QPT) on a quantum noise process of a target quantum system, to obtain dynamical maps of the quantum noise process, wherein the QPT involves at least one measurement of the target quantum. The method further includes extracting transfer tensor maps (TTMs) of the quantum noise process from the dynamical maps; and analyzing the quantum noise process according to the TTMs. The TTM is used for representing a dynamical evolution of the quantum noise process to reflect the law of evolution of the dynamical maps of the quantum noise process over time.

Abstract: For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.

Abstract: Disclosed are a method for verifying a convolutional neural network model and a device thereof. The method for verifying the convolutional neural network model includes (a) generating a polynomial circuit equation for a first configuration of a plurality of configurations configuring the convolutional neural network model; (b) generating a first commitment value and a first proof value by applying a zero-knowledge proof scheme based on the polynomial circuit equation; (c) generating an arithmetic circuit equation for a second configuration of the plurality of configurations; (d) generating a second commitment value and a second proof value by applying a zero-knowledge proof scheme based on the arithmetic circuit equation; and (e) generating a connection proof value connecting the first commitment value and the second commitment value.

Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: A method for analyzing disaster prevention and mitigation effectiveness of an ecological seawall is provided, including: performing seawall ecologicalization on a target seawall; establishing three-dimensional space hydrodynamic force for the target ecological seawall; simulating wave climbing on a dike body and a wave overtopping on a dike top of the target ecological seawall to obtain a wave overtopping index; calculating wave-flow bottom shear stress of the target ecological seawall, establishing a sediment movement model, and calculating suspended load and bed load sediment transportation volumes; calculating the change index of coastal bed surface according to the suspended load and bed load sediment transportation volumes, and determining a development index of tidal flats in front of dike of the target ecological seawall according to the change index; and calculating the disaster prevention and mitigation effectiveness grade of the target ecological seawall according to the wave overtopping index and t

Abstract: A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a retention circuit. The retention circuit includes a clock gating enabled register, a first AND gate connected to a clear pin of the register, and a second AND gate connected to a chip enable pin of the register. The method further includes compiling, by a processing device, the circuit design.

Abstract: Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.