Abstract: Phase abstraction may be utilized to increase efficiency of model checking techniques. A liveness property may be checked in respect to a phase abstracted model by modifying the liveness property in accordance with the phase abstracted model. A fairness property may be modified to ensure that the fairness property is held by the model checker. A counter-example produced by a model checker is modified to be in accordance to an original model. The counter-example comprises a repetitive behavior. The counter-example may be modified to shorten the repetitive behavior or to apply the repetitive behavior in an earlier cycle of the counter-example.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating a computer program. A system configured to practice the method identifies a set of executable instructions at a first location in an instruction section of the computer program and identifies a second location in a data section of the computer program. Then the system moves the set of executable instructions to the second location and patches references in the computer program to the set of executable instructions to point to the second location. The instruction section of the computer program can be labeled as _TEXT,_text and the data section of the computer program is labeled as _DATA,_data. The set of executable instructions can include one or more non-branching instructions optionally followed by a branching instruction. The placement of the first and second locations can be based on features of a target computing architecture, such as cache size.

Abstract: Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits.

Abstract: A method for computing a fast Fourier transform (FFT) in a parallel processing structure uses an interleaved computation process. In particular, the interleaved FFT computation process intertwines the output of two different shifted Fourier matrices to obtain a Fourier transform of an input vector. Next, an even-odd extension process is applied to the transformed input vector, whereupon various terms are grouped in a computational tree. As such, the resulting segmentation of the computation allows the fast Fourier transform to be computed in a parallel manner.

Abstract: A method for generating authentication code for web service resources. The method includes receiving a selection of a resource method, where the resource method defines a method for interacting with a resource associated with a web service. The method further includes determining an authentication scheme for the resource method, where the authentication scheme defines an authentication mechanism required during execution of the resource method to enable interaction with the resource. The method further includes generating authentication code for the resource method using the authentication scheme, where the authentication code enables a user executing the resource method to interact with the resource.

Abstract: Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.

Abstract: A method for optimizing the object code of a program is disclosed. A compiler generates, respectively, first and second object code segments for first and second source code segments of the program. If the two object code segments are determined to be identical, the compiler generates first and second debugging information entries in a compilation unit of the program and both entries include information for locating the first object code segment. The compiler inserts two entries into a call table in the compilation unit, each entry including information for locating a respective call site that invokes a respective source code segment within a call stack of the program and information for locating a respective debug information entry. The call table is used for associating an operation within the first object code segment with one of the first and second source code segments at runtime.

Abstract: A method for debugging the object code of a program is disclosed. While executing an object code segment on an information processing device, a debugger receives a location identifier associated with the object code segment and identifies a call site within a call stack of the program using the location identifier. The call site is responsible for invoking the execution of the object code segment. Next, the debugger scans a call table for an entry of the call site that includes information for locating a debugging information entry within a compilation unit of the program. The debugger retrieves the debugging information entry from the compilation unit using the location information and identifies a unique one of multiple different source code segments as the one corresponding to the object code segment using a source code segment identifier in the debugging information entry.

Abstract: The system and method in one aspect allow understanding of Boolean expressions by representing them graphically as a flow of information. NOTs are represented as switches in the flow, capturing the original structure of the expression as written by the user. Verification of those expressions with live data is also enabled.