Abstract: A vacuum orientation module for a substrate processing system is described. The module includes at least a first vacuum orientation chamber, comprising: a vacuum chamber; a first transportation track within the vacuum chamber, the first transportation track having a first support structure and a first driving structure and defining a transportation direction; an orientation actuator to change the substrate orientation between a non-vertical orientation and a non-horizontal orientation, the vacuum chamber has a first pair of two slit openings, particularly essentially vertical slit openings, at opposing side walls of the vacuum chamber in the transportation direction; and a second transportation track within the vacuum chamber, the second transportation track having a second support structure and a second driving structure extending along the transportation direction, the vacuum chamber has a second pair of two slit openings at the opposing side walls of the vacuum chamber.

Abstract: An optical device includes, in sequence, a surface formed of a metal oxide, a samarium oxide-containing layer in contact with the surface formed of a metal oxide, and a magnesium fluoride-containing layer in contact with the samarium oxide-containing layer so as to suppress optical absorption resulting from high-rate sputter deposition of a magnesium fluoride-containing layer on a surface formed of a metal oxide.

Abstract: The present disclosure relates to a method for chemical vapour deposition on a substrate, the method comprising a precursor step and a reactant step, wherein the precursor step comprises chemisorbing a layer of precursor molecules on the substrate (170), and wherein the reactant step comprises adding to at least part of the substrate (170) surface species able to reduce the precursor molecule, whereby at least a part of the reduced precursor molecule is deposited on the substrate (170) surface, characterized by applying by means of a voltage source (130) a positive bias to at least part of the substrate (170) surface during at least part of the reactant step, wherein the step of adding the reducing species comprises providing by means of an electron source (150) electrons as free particles, whereby during the reactant step a closed electrical circuit is formed as the free electrons are transmitted to the substrate (170) surface.

Abstract: An alignment method includes directing an illumination beam with a first polarization state to form a diffracted beam with a second polarization state from an alignment target, and passing the diffracted beam through a polarization analyzer. The alignment method further includes measuring a polarization state of the diffracted beam and determining a location of the alignment target from the measured polarization state relative to its initial polarization state. The alignment target includes a plurality of diffraction gratings with a single pitch and two or more duty cycles, wherein the pitch is smaller than a wavelength of the illumination beam, and the location of the alignment target corresponds to the duty cycle of the diffraction grating.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A method of tie bar removal is provided. The method includes forming a leadframe including a tie bar and a flag. The tie bar extends from a side rail of the leadframe and has a distal portion at an angle different from a plane of the flag. A semiconductor die is attached to the flag of the leadframe. A molding compound encapsulates the semiconductor die, a portion of the leadframe, and the distal portion of the tie bar. The tie bar is separated from the molding compound with an angled cavity remaining in the molding compound.

Abstract: An imaging element including: a photoelectric conversion layer including a compound semiconductor material; a contact layer disposed to be stacked on the photoelectric conversion layer and including a diffusion region of first electrically-conductive type impurities in a selective region; a first insulating layer provided to be opposed to the photoelectric conversion layer with the contact layer interposed therebetween and having a first opening at a position facing the diffusion region; and a second insulating layer provided to be opposed to the contact layer with the first insulating layer interposed therebetween and having a second opening that communicates with the first opening and is smaller than the first opening.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a plurality of auxiliary pixel driving circuits. Each of the auxiliary pixel driving circuits includes transistors, and each of the transistors includes an active layer and an insulation layer. The display panel is defined with first dummy holes in a transition display area, and the first dummy holes penetrate a part of the insulation layer away from the active layer in order to reduce difference in electrical properties between the auxiliary pixel driving circuits through the first dummy holes, thereby achieving display uniformity of the display panel.

Abstract: The present invention relates to an electrical component for a microelectromechanical systems (MEMS) device, in particular, but not limited to, an electromechanical actuator.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.

Abstract: An apparatus and method is provided for coating a surface of a material with a film of porous coordination polymer. A first substrate having a first surface to be coated is positioned in a processing chamber such that the first surface is placed in a substantially opposing relationship to a second surface. In some embodiments, the second surface is provided by a wall of the processing chamber, and in other embodiments the second surface is provided by a second substrate to be coated. The first substrate is held such that a gap exists between the first and second surfaces, and the gap is filled with at least one reaction mixture comprising reagents sufficient to form the crystalline film on at least the first surface. A thin gap (e.g., having a thickness less than 2 mm) between the first and second surfaces is effective for producing a high quality film having a thickness less than 100 ?m.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A method for manufacturing a wavelength conversion member, includes: providing a wavelength conversion layer having a phosphor-containing portion and a light reflecting portion surrounding the phosphor-containing portion, and the wavelength conversion layer having an upper surface, a bottom surface and at least one side surface; forming a light-blocking film on the upper surface of the wavelength conversion layer; and removing a part of the light-blocking film by laser processing to expose at least a part of the phosphor-containing portion from the light-blocking film.

Abstract: Provided is a semiconductor film having a corundum-type crystal structure composed of ?-Ga2O3 or an ?-Ga2O3 solid solution and the crystal defect density on at least one surface of the semiconductor film is 1.0×106/cm2 or less.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: A film thickness measurement apparatus includes: a stage that places a substrate having a film formed thereon and measures a thickness of the film in-situ in a film forming apparatus; a film thickness meter including a light emitter that emits light toward the substrate disposed on the stage and a light receiving sensor that receives the light reflected by the substrate for measuring the thickness of the film in-situ; a moving mechanism including a multi-joint arm that moves an irradiation point of the light on the substrate; a distance meter that measures a distance between the light receiving sensor and the irradiation point on the substrate; and a distance adjustor that adjusts the distance between the light receiving sensor and the irradiation point on the substrate.