Abstract: A semiconductor device according to the invention comprises: a first semiconductor layer having a low impurity concentration formed on a semiconductor substrate; a second semiconductor layer of a first conductivity type formed on the first semiconductor layer and forming a heterojunction therewith; an emitter region and a collector region formed in the first and second semiconductor layers; and a semiconductor region of a second conductivity type formed in at least the second semiconductor layer between the emitter region and the collector region, wherein two-dimensional electron gas layers, induced in portions of the first semiconductor layer adjacent to the heterojunction and between the emitter region and the semiconductor region and between the collector region and the semiconductor region, are used as current paths, and a virtual base region is formed in the first semiconductor layer below the semiconductor region by majority carriers injected from the semiconductor region into the first semiconductor la

Abstract: A bipolar power transistor having a plurality of elongated emitter parts connected to a common emitter metallization is provided with a shaped resistive region between the emitter parts and the emitter metallization, in order to compensate for differences in the resistance presented by the metallization itself.

Abstract: An integrated triac structure with diac control is provided on a common substrate. The diac is connected to the gate of the triac by a common metallization on the integrated substrate. The diac has a lateral structure with two metallizations on the same face of the substrate. It is separated from the triac by a passivated furrow 16 deeper than the gate region of the triac.

Abstract: A thin film static induction transistor comprises a first n type semiconductor layer provided on an insulative substrate and a second n type semiconductor layer mounted on the first layer. The second layer includes a first region having a first level top wall and a second region having a second level top wall lower that the first level top wall. The first and second regions are alternately arranged. A third semiconductor layer is provided on the first level top wall. A recess is formed which includes side walls of the third layers, side wall of the first regions and the second level top wall. A fourth semiconductor layer is deposited on the inner wall of the recess, and a gate electrode is provided on the fourth layer. The fourth layer consists of an intrinsic semiconductor layer or a semiconductor layer having a lower impurity concentration than the second layer.

Abstract: A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

Abstract: A semiconductor device has a deep control grid. A silicon substrate is grooved. The side walls and the bottom of the grooves are oxidized. Under the bottom of the grooves a dopant is implanted and diffused. A main metalization covering the grooved face makes a contact with the surface thereof and the parts of this metalization falling in the grooves does not cause any parasitic effect as the walls and the bottom of the grooves are insulated.

Abstract: At least one set of light emitting element, converting an electric signal into an optical signal, and light receiving element, converting an optical signal into an electric signal, is integrated into one chip of semiconductor device.

Abstract: A high speed photoconductive detector is disclosed which comprises two interdigital electrically conducting electrodes formed on a photoconductive layer. The device speed and sensitivity are improved by using a double-heterostructure configuration comprising an active layer formed on an isolation layer in turn formed on a supporting substrate. A passivation layer is formed on the active layer. This configuration confines the generated carriers to the active layer. Consequently, current will be induced under optical illumination due to photo-carrier generation. This interdigitated geometry allows for a large device cross-section and small carrier transit distance.

Abstract: A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.

Abstract: A piezoelectric double diffusion MOS structure in which three gates are inserted in the CVD oxide element. These gates are overlapped layers of CVD polysilicon on top of the ZnO and are capacitively coupled to the silicon substrate. The charge is placed on the middle floating gate and is retained because of the oxide layers which separate the gates. A program erase, gate is provided for discharging the floating gate and to set the modes.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The device comprises a GaAs semiconductor body, a source and a drain region formed in the semiconductor body, a channel region placed between the source and drain regions, a source and a drain electrodes provided by patterning treatment onto the surfaces of the source and drain regions and making ohmic contact thereto, and a gate electrode provided onto the surface of the channel region and consisting of a W-Al alloy.

Abstract: A microminiature valve having a multilayer integral structure formed on a semiconductor substrate. The valve comprises a semiconductor substrate having inlet and outlet apertures and a raised valve seat. The substrate is overlayed with a nonporous top layer and an intermediate layer. The central portion of the intermediate layer is preferentially etched away to form an enclosed chamber connecting said inlet and outlet ports. The unetched portion of said intermediate layer peripherally supports said top layer above the valve seat. An electrically conductive electrode disposed on the unsupported portion of the top layer permits it to be electrostatically deflected to engage the valve seat and close the valve.

Abstract: The invention provides a semiconductor device in which an insulating film or a semiconductor film is firmly bonded with a metal silicide film, and also provides a method for manufacturing the same. The semiconductor device has a semiconductor substrate with an insulating film or a semiconductor film formed thereon, a carbon layer formed on the insulating film or the semiconductor film, and a metal silicide film formed on the carbon layer. Carbon atoms are thermally diffused by heating from the carbon layer into the insulating film or the semiconductor film and into the metal silicide film.

Abstract: Bipolar transistors and other electronic structures are fabricated on a gallium arsenide (GaAs) substrate to form an integrated circuit device. This integrated circuit device is made possible by development of an ion implant technique which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. The use of an ion implant technique avoids the difficult problems encountered in diffusion methods, and, due to the precise control available with ion implantation, makes possible the fabrication of IC quality transistors consistently over a substrate. This same control enables the fabrication of integrated circuits with improved device packing density and reduced parasitic parameters.

Abstract: A unipolar hot-electron or hot-hole transistor has its base region and/or collection region electrically contacted and extended to the semiconductor body surface by a metal-silicide region which extends through a silicon surface region belonging to either the transistor emitter or the emitter-base barrier. The metal-silicide region forms an isolating Schottky barrier with an adjacent semiconductor portion. Preferably, the surface region is divided into separate first and second portions by the base-contacting metal-silicide region, with the emitter-base barrier and base-collector barrier terminating at one or more sides in this metal-silicide region. The isolating Schottky barriers are good quality unipolar diodes, thus avoiding minority charge carrier storage effects in these unipolar transistors, while the metal-silicide region can form good ohmic contacts to highly-conductive base and collector regions which typically comprise a high-doped semiconductor layer or a metal-silicide layer.