Abstract: A computational field programable architecture targeted for compute intensive applications. The architecture is hierarchical and includes, for implementation of data path circuits, clusters of programable logic blocks that are designed to provide area-efficient realization of common arithmetic structures such as adders, subtracters and multipliers. The architecture includes a LUTb cluster for implementing the control part of a circuit. The programable logic blocks each include a stack of programable bit-slice logic elements each having 2 data inputs and a single data output, and a 1-bit full adder circuit. The bit slice logic elements allow bit-wise logic operations to be carried out and the programable logic blocks also include comparator logic to enable comparison operations to be performed. The bit slice logic elements each include a DFF at their output, and the DFFs in a programable logic blocks can be combined to form a register.