Abstract: A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus. Data signals are routed between the various blocks of the microprocessor by selectively interconnecting the three buses in response to control signals provided by ALU and control programmable logic arrays (PLA). The ALU and control PLA's decode program instructions loaded in instruction register (IR) to provide the appropriate control signals for executing each instruction.

Abstract: A microprocessor, having a memory element containing a plurality of multi-bit instruction words, an arithmetic logic (ALU) unit coupled to the memory element and responsive to at least a portion of each of the instruction words for performing data manipulations, and a controller for generating address signals that are communicated to the memory element to cause sequential access of the instruction words, includes a storage element that interconnects certain of the signal lines that communicate the instruction words to the ALU to the controller. In response to a first predetermined instruction word the storage element receives and stores the portion of the instruction word being conducted to the ALU. In response to a second predetermined instruction word, the content of the storage element is transferred to the controller to form an address signal.

Abstract: A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction is executed in a sequence of microstates which are generated by selecting an entry point for the first address in a control ROM then continuing with a series of jumps and/or further entry points determined by the instruction and by the current state of the microprocessor. Improved circuitry is provided for selecting the entry point using a minimum of space on the chip by detecting the position of the leading 1 bit. Thus an instruction set can be used in which different groups of instructions have different numbers of leading zero bits.

Abstract: A serial-to-parallel converter receives serial data bits forming serial input words and serial word synchronizing pulses indicating the length of the serial input words. A parallel clock signal is generated synchronously with an integer number of serial word synchronizing pulses. The input data is sequentially supplied via a direct data path to an output storage means. A synchronous counter counts the received consecutive serial data bits and in response to each count a decoder sequentially enables one respective output storage means to store therein one data bit. The stored data is released simultaneously from the output storage means in form of a parallel word in response to the parallel clock signal. Means for changing the length of the parallel output word are provided.

Abstract: The apparatus comprises a plurality of vacuum operated sheet moving organs mounted on a rotating counting disc which activates a counter each time a sheet is engaged by one of the sheet removing organs and moved from a first to a second position during the counting cycle, the counter actuating mechanism including a vacuum switch to inhibit the actuation of the counter if the vacuum to the sheet moving organs falls below a predetermined level due to the failure of the sheet moving organs to make proper contact with the sheets being counted, and a delay mechanism operative to prevent the vacuum switch from inhibiting actuation of the counter in the event of a momentary drop in the vacuum level upon improper initial contact of the sheet moving organs with the sheets but where proper contact is established before a predetermined position in the counting cycle is reached.