Abstract: Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism.To protect information in segments shared by several processes from misuse by one of these processes a ring protection hardware system is utilized. There are four ring classes numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may legally call the procedure. Also maximum write and read ring numbers specify the maximum ring numbers for which a write and/or read operation is permitted.

Abstract: A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern.

Abstract: This invention relates to controls for a control store made of plural modules which operate in an overlapped continuous manner, wherein the modules are cycled in a fixed sequence.This invention particularly relates to a novel next address generation and handling means for a control store using time interleaved modules.

Abstract: A PROM programmer programs an array of PROMs mounted on a circuit board. The PROM chips are selectively addressed by energization of the respective chip with a high write voltage or a low read voltage while an individual cell is addressed. A control unit controls the flow of data into and out of the circuit board via a memory buffer unit.

Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor incorporates practical data-flow processing of a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnection that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.

Abstract: A method for substituting one memory module for another, faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called, and responds to the address of the faulty module whenever the latter is called.

Abstract: A digital computer may be structured in two separate sections, one of which performs the execution of arithmetic and conditional instructions, and the other which contains and performs operations upon data structures. The organization of the structure processing section of a digital computer is described herein. The structure processing section maintains data structures represented as acyclic directed graphs and is viewed as a functional unit by the instruction processing section; that is, instructions specifying structure operations are sent to the section, and any resulting values are returned to the instruction processing section. The organization of the structure processing section permits the simultaneous processing of many structure operations.

Abstract: The peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral system data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register, and the control register are transferred via the output bus to the data bus buffers.

Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The processor operates in a data-driven fashion; that is, an instruction of a program in the processor is enabled for execution upon the arrival of all required operands, and upon being executed, sends copies of the resulting value to all instructions which require it for their execution. The processor incorporates a form of deadlock prevention between the instructions of a data-flow program, allowing a value to be generated by an instruction and sent to the successor instructions in the computation only when those instructions are ready to receive the value. The incorporation of this mechanism prevents the possibility of conflict between successive stages of a pipelined computation and between successive iterations of an iterative computation.

Abstract: This disclosure describes a novel computer system in which a large capacity, serial storage medium, on which standardized programs and data banks can be economically recorded, as the primary memory component. The operating software program is not transferred into core memory, as is typical of present day computers, but remains resident in the memory on which it has been prerecorded. The resulting system is lower in cost, and especially suitable for using standardized programs which can be distributed in machine compatible form at modest cost.

Abstract: Packet communication is used in the architecture of a memory system capable of processing many independent memory transactions concurrently. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.

Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.

Abstract: A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.

Abstract: A data handling module connects to the memory of a programmable controller and operates to periodically steal memory cycles from the controller processor to read data out of the memory and write data into it. The data handling module includes a microprocessor which is programmed to perform a number of functions. The function to be performed is indicated by a control status register which is set by the control program and which is periodically examined by the data handling module. The status of the data handling module is also indicated by a register which is examined by programmable controller instructions. In response to directions indicated by the control status register, data files may be transferred between a data file storage and an active data file storage area and messages may be coupled to a TTY which connects to the data handling module.

Abstract: The data address portions of a set of computer instructions are scrambled in accordance with a predetermined cipher key before the instructions are loaded into the instruction memory. The instructions with the scrambled data address portions are then loaded into the instruction memory at addresses corresponding to the original program sequence. The data involved in the program is loaded into a separate data memory at the addresses specified in the original unscrambled program. An unscrambler circuit which operates in accordance with the cipher key is coupled in series with the data memory address input conductors and is mounted on the data memory unit and is encapsulated therewith to prevent anyone from examining the unscrambler to determine the cipher key or from electrically interrogating the unscrambler in such a manner as to determine the cipher key.

Abstract: An arrangement for sharing file information among plural processes in a multiprogrammed computing system. Source program file declarations are compiled into file control structures which are placed in skeletal segments, the segments forming units of potential sharing between active processes. Those segments which contain file control structures are placed in either the address space of (1) all processes, (2) related processes, or (3) a single process, depending upon the declared sharing level of the file. Job control language (JCL) commmands are expanded into JCL file control structures and merged with the source language structures to form a file request control structure. This request may be compared against a catalog of existing external files, a check being made to insure that the account on whose behalf a computing job is requesting file assignment is authorized to obtain the requested access to the file.

Abstract: A digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunctioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subsequently addressed.

Abstract: A system tool for electronically generating a machine directory entity having a binary tree relationship. The method generates the directory entity directly from a sequence of input keys without using an intermediate stack. The input key sequence may be sorted or unsorted; but if sorted (whether ascending or descending), the system tool is made more efficient. The directory entity is used by the machine to address objects which may be found within the confines of the machine.Unique connectors called invertible edges, are generated in the machine organization of the directory entity being generated.

Abstract: A data processing system includes as part of its power circuits, a number of converter circuits, each coupled to a different one of the power supply units which are to provide different voltages for distribution and use throughout the system. Each of the power supply circuits furnish a 24 volt dc power confidence signal to a central ac power input entry panel which applies the power confidence signals to the converter circuits. Each converter circuit includes an optically coupled isolator circuit which converts the 24 volt dc signal to a noise free low voltage logic level suitable for utilization by the low level high speed logic circuits included within the system. The output noise free low voltages provided by the converter circuits are in turn applied to a corresponding number of confidence input lines of a system interface unit which includes a plurality of ports, each port connected to a different module within the data processing system.

Abstract: A programmable automatic controller for operating machines having a plurality of components which operate in a timed or sequential relationship with one another. The controller includes a timing means for generating cycle clock pulses in synchronism with the operation of the machine, wherein the cycle clock pulses provide an instantaneous indication of the time elapsed in each cycle of operation of the machine. A COM/MOS running storage means stores the relative times during each cycle of machine operation when each of the plurality of machine components are to be enabled and/or inhibited. When the time elapsed in a cycle corresponds to a component actuating time stored in the running storage, an actuating signal is generated by a comparator. This signal is coupled to a machine component addressing arrangement which provides a component enable or inhibit command signal to the addressed component whose actuating time compared to the cycle time lapsed.