Abstract: A data output buffer of a semiconductor memory device having a data output driver comprised of a pull-up transistor and a pull-down transistor includes a precharging circuit for precharging a gate terminal of the pull-up transistor of the data output driver to a power supply voltage level. Precharging the output driver reduces the load on the pumping voltage generator. This feature, together with precharging the pumping voltage generator itself, allow clocking the pumping voltage generator at a reduced clock rate to reduce power consumption without compromising operating speed of the memory device.

Abstract: A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the event of failure of that antifuse. The method includes programming the device under control of a computer which can recalculate routes in the event of an antifuse which fails to program. Preferably the initial routing distributes unused wiring segments through the chip to be available for routing around a failed antifuse. When a failure occurs, the method includes determining an alternative route around every failed antifuse. The alternative route may be established directly after the antifuse has failed or after all initially selected antifuses have been programmed.

Abstract: A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one of a pair of complementary input voltages. The floating gate devices also have complementary threshold voltages such that packets of charge are produced from the synapse cells that are proportional to the difference between the input and voltage threshold. The charge packets are accumulated by the pairs of column lines in the array.