Patents Examined by Jarrett J. Stark
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Patent number: 11586899Abstract: A method of fabricating a neuromorphic device includes forming a variable-resistance layer between a first terminal and a second terminal, the variable-resistance layer varies in resistance based on an oxygen concentration in the variable-resistance layer. The method further includes forming an electrolyte layer over the variable-resistance layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. The method further includes forming a gate layer over the electrolyte layer to apply a voltage on the electrolyte layer and the variable-resistance layer, the gate layer formed using an oxygen scavenging material.Type: GrantFiled: June 10, 2019Date of Patent: February 21, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teodor Krassimirov Todorov, Jianshi Tang, Douglas M. Bishop, John Rozen, Takashi Ando
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Patent number: 11588095Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.Type: GrantFiled: May 24, 2019Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hui Lin, Chun-Ren Cheng, Shih-Fen Huang, Fu-Chun Huang
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Patent number: 11581399Abstract: Methods and semiconductor circuits are described in which a polysilicon resistor body is formed over a semiconductor substrate. A first dopant species is implanted into the polysilicon resistor body at a first angle about parallel to a surface normal of a topmost surface of the polysilicon resistor body. A second dopant species is implanted into the polysilicon resistor body at a second angle greater than about 10° relative to the surface normal. The combination of implants reduces the different between the temperature coefficient (tempco) of resistance of narrow resistors relative to the tempco of wide resistors, and brings the tempco of the resistors closer to a preferred value of zero.Type: GrantFiled: June 30, 2020Date of Patent: February 14, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Mahalingam Nandakumar
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Patent number: 11569101Abstract: A fluid supply device and a fluid supply method capable of stably supplying a supercritical fluid includes a fluid supply device for supplying a fluid in a liquid state before being changed to a supercritical fluid toward a processing chamber. The fluid supply device comprises a condenser that condenses and liquefies a fluid in a gas state, a tank that stores the fluid condensed and liquefied by the condenser, a pump that pressure-feeds the liquefied fluid stored in the tank toward the processing chamber, and a heating means provided to a flow path communicating with a discharge side of the pump and for partially changing the liquid in the flow path to a supercritical fluid.Type: GrantFiled: July 31, 2018Date of Patent: January 31, 2023Assignees: FUJIKIN INCORPORATED, TOKYO ELECTRON LTD.Inventors: Toshihide Yoshida, Yukio Minami, Tsutomu Shinohara
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Patent number: 11569277Abstract: There is disclosed a semiconductor device including: a substrate; a plurality of first electrodes arranged away from each other with gaps on the substrate; a first intermediate layer arranged on each of the plurality of first electrode; a second intermediate layer, at least a part of which is arranged on each of the gaps of the plurality of first electrodes; a photoelectric conversion layer arranged on the first intermediate layer and the second intermediate layer; and a second electrode arranged on the photoelectric conversion layer. A content of oxygen on a molar basis in the second intermediate layer is higher than a content of oxygen on a molar basis in the first intermediate layer.Type: GrantFiled: September 1, 2020Date of Patent: January 31, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Takayuki Sumida, Yoshinori Tateishi, Takahiro Yajima
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Patent number: 11569104Abstract: A substrate processing apparatus includes a temperature detector and a controller. The temperature detector detects a temperature of processing liquid before the temperature of the processing liquid in pre-dispensing in progress reaches a target temperature. The controller sets discharge stop duration of the processing liquid in the pre-dispensing based on target temperature prediction duration. The target temperature prediction duration is prediction duration until the temperature of the processing liquid reaches the target temperature from a detection temperature. The detection temperature is the temperature of the processing liquid detected by the temperature detector before the temperature of the processing liquid reaches the target temperature. The target temperature prediction duration is determined based on a temperature profile.Type: GrantFiled: December 28, 2018Date of Patent: January 31, 2023Inventors: Takashi Ota, Masayuki Hayashi, Jiro Okuda, Akihiro Nakashima
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Patent number: 11563050Abstract: Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit that accumulates an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit that transfers an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit that couples potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit that transfers an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit and transfers an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit that reduces light to enterType: GrantFiled: February 24, 2017Date of Patent: January 24, 2023Assignee: SONY CORPORATIONInventors: Tomohiko Asatsuma, Minoru Ishida
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Patent number: 11552236Abstract: A method for adjusting a resonance frequency of a qubit in a quantum mechanical device includes providing a substrate having a frontside and a backside, the frontside having at least one qubit formed thereon, the at least one qubit comprising capacitor pads; and removing substrate material from the backside of the substrate at an area opposite the at least one qubit to alter a capacitance around the at least one qubit so as to adjust a resonance frequency of the at least one qubit.Type: GrantFiled: January 24, 2020Date of Patent: January 10, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas M. Gill, Martin O. Sandberg, Vivekananda P. Adiga, Jason S. Orcutt, Jerry M. Chow
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Patent number: 11552240Abstract: A sensor is disclosed which includes a piezoelectric layer, a piezoresistive layer, one or more electrode layers coupled to the piezoelectric layer and to the piezoresistive layer, the piezoelectric layer configured to provide an electrical signal in response to application of a dynamic disturbance, and the piezoresistive layer configured to provide a change in resistivity in response to application of a static disturbance.Type: GrantFiled: September 16, 2019Date of Patent: January 10, 2023Assignee: Purdue Research FoundationInventors: Mukerrem Cakmak, Armen Yildirim, Rahim Rahimi, Saeed Mohammadi, Ali Shakouri
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Patent number: 11552239Abstract: A superconducting quantum mechanical device includes first, second, third and fourth Josephson junctions connected in a bridge circuit having first, second and third resonance eigenmodes. The device also includes first and second capacitor pads. The first and second capacitor pads and the bridge circuit form a superconducting qubit having a resonance frequency corresponding to the first resonance eigenmode. The device further includes first and second resonator sections. The first and second resonator sections and the bridge circuit form a resonator having a resonance frequency corresponding to the second resonance eigenmode. The device also includes a source of magnetic flux arranged proximate the bridge circuit. The source of magnetic flux is configured to provide, during operation, a magnetic flux through the bridge circuit to cause coupling between the first, second and third resonance eigenmodes when the third resonance eigenmode is excited.Type: GrantFiled: November 27, 2019Date of Patent: January 10, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Baleegh Abdo
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Patent number: 11545381Abstract: Provided is a substrate transferring method which is capable of accurately mounting a substrate at a desired rotation angle. In order to eliminate a misalignment of a wafer W in a rotational direction in a vacuum process chamber, which is caused by a variation in a transfer distance of the wafer W, the wafer W is mounted on a stage while being offset from the center of the stage in a load lock chamber and an angle of rotation of the wafer W with respect to a fork when a transfer arm receives the wafer W is changed.Type: GrantFiled: February 23, 2017Date of Patent: January 3, 2023Assignee: TOKYO ELECTRON LIMITEDInventor: Keisuke Kondoh
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Patent number: 11537866Abstract: The present disclosure relates to semiconductor structures and, more particularly, to optical neuro-mimetic devices and methods of manufacture. The structure includes: a plurality of photodetectors and electrical circuitry that converts photocurrent generated from the photodetectors into electrical current and then sums up the electrical current to mimic neural functionality.Type: GrantFiled: May 21, 2020Date of Patent: December 27, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob, Yusheng Bian, Michal Rakowski
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Patent number: 11538864Abstract: A double-sided display panel and a manufacture method thereof, and a double-sided display device are provided. The double-sided display panel includes a first display layer and a second display layer which are disposed opposite to each other; the first display layer includes a plurality of first pixel units and a plurality of first light adjusting components; the second display layer includes a plurality of second pixel units and a plurality of second light adjusting components; colors of light transmitted by a first light adjusting component and a second light adjusting component which are correspondingly stacked are different.Type: GrantFiled: March 21, 2019Date of Patent: December 27, 2022Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.Inventors: Zongxiang Li, Liqing Yao, Jiamin Liao, Xinmao Qiu, Wenchang Tao, Zhendian Wu, Dahai Li, Guichun Hong, Changhong Shi
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Patent number: 11538980Abstract: An actuator device has an electroactive polymer actuator (35) and an integrated piezoelectric transformer (30) whose primary side (32) and secondary side (34) are formed from different electroactive polymer materials. At least the secondary side (34) of the transformer shares a piezoelectric electroactive polymer layer (36) with the electroactive polymer actuator, so that lower external voltages can be applied to the device.Type: GrantFiled: June 7, 2017Date of Patent: December 27, 2022Assignee: KONINKLIJKE PHILIPS N.V.Inventors: Achim Hilgers, Daan Anton Van Den Ende, Mark Thomas Johnson, Roland Alexander Van De Molengraaf
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Patent number: 11532515Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.Type: GrantFiled: October 9, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia
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Patent number: 11532492Abstract: A substrate processing apparatus includes a liquid processing module, including a carry-out/in port of a substrate, in which a first liquid processing device and a second liquid processing device provided at a position farther from the carry-out/in port than the first liquid processing device is are provided; and a transfer device configured to carry the substrate out from and into the liquid processing module. The first liquid processing device performs a first liquid processing on the substrate. The second liquid processing device performs a second liquid processing on the substrate before or after the first liquid processing. The transfer device includes a substrate holder configured to be moved back and forth in a first horizontal direction, and carries the non-processed substrate into the first liquid processing device through the carry-out/in port and carries the processed substrate out from the first liquid processing device through the carry-out/in port.Type: GrantFiled: March 26, 2020Date of Patent: December 20, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Katsuhiro Morikawa, Masami Akimoto
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Patent number: 11527568Abstract: Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit that accumulates an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit that transfers an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit that couples potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit that transfers an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit and transfers an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit that reduces light to enterType: GrantFiled: February 24, 2017Date of Patent: December 13, 2022Assignee: SONY CORPORATIONInventors: Tomohiko Asatsuma, Minoru Ishida
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Patent number: 11521970Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.Type: GrantFiled: October 5, 2020Date of Patent: December 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiang-Ku Shen, Chih Wei Lu, Hui-Chi Chen, Jeng-Ya David Yeh
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Patent number: 11508845Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.Type: GrantFiled: September 22, 2020Date of Patent: November 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chen-Liang Chu, Ta-Yuan Kung, Ker-Hsiao Huo, Yi-Huan Chen
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Patent number: 11508574Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a stage to have a plurality of pins to hold a semiconductor substrate having a first surface on which a film to be etched is formed and a second surface positioned on an opposite side to the first surface; a nozzle to eject a liquid chemical toward the first surface of the semiconductor substrate from above the stage; and an optical measurer to radiate light toward the second surface of the semiconductor substrate from a side of the stage during ejection of the liquid chemical, and to measure a displacement amount of the semiconductor substrate based on a state of reception of light reflected on the second surface.Type: GrantFiled: March 6, 2020Date of Patent: November 22, 2022Assignee: Kioxia CorporationInventor: Hiroyasu Iimori