Patents Examined by Jason W Blust
  • Patent number: 11977763
    Abstract: Disclosed are techniques that provide for eventually-complete backups, and restoration thereof. For example, such methods, computer program products, and computer systems can include initiating a backup operation (where the backup operation is configured back up a dataset), detecting termination of the backup operation, detecting termination of the backup operation, and determining whether the backup operation backed up the dataset completely. In response to a determination that the backup operation did not backup the dataset completely, generating an indication that the backup is not complete. In response to a determination that the backup operation did not backup the dataset completely, generating an indication that the backup is complete.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: May 7, 2024
    Assignee: Veritas Technologies LLC
    Inventors: Vaijayanti Rakshit Bharadwaj, Chirag Dalal
  • Patent number: 11966301
    Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Stephen Wu, Prathamesh Deshpande, Manan Patel
  • Patent number: 11960733
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a plurality of control cores configured to control a plurality of memory devices, respectively, a host core configured to allocate write requests received from a host to each of the plurality of control cores based on predefined criteria, and a shared memory configured to be accessed by the host core and the plurality of control cores, wherein, in response to occurrence of a sudden power-off, the host core is further configured to store, in the shared memory, dump information including information about logical addresses corresponding to the write requests, and wherein a first control core is further configured to store, in a memory device controlled by the first control core, the dump information of a second control core associated with the first control core.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventor: Jae Il Lee
  • Patent number: 11960403
    Abstract: System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony M. Brewer
  • Patent number: 11954033
    Abstract: A method includes, in a cache directory, storing an entry associating a memory region with an exclusive coherency state, and in response to a memory access directed to the memory region, transmitting a demote superprobe to convert at least one cache line of the memory region from an exclusive coherency state to a shared coherency state.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: April 9, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Balakrishnan, Amit Apte, Ann Ling, Vydhyanathan Kalyanasundharam
  • Patent number: 11934664
    Abstract: Aspects of a storage device are provided that provide power control and power loss handling in a RAID system. The storage device may include a memory, a controller coupled to the memory, a power management circuit coupled to the memory and the controller, and a rechargeable battery coupled to the power management circuit. The controller may receive power supplied by a RAID controller, receive a notification of a loss in power supplied to another storage device, and cause the power management circuit to detect a charge of the rechargeable battery in response to the notification. The power management circuit may also detect another loss in power supplied by the RAID controller, cause the controller to send a message to the RAID controller indicating the loss in power, and receive power from the RAID controller in response to the message. As a result, UGSDs in RAID may be detected and addressed.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Nian Yang, Judah Gamliel Hahn
  • Patent number: 11934705
    Abstract: Techniques for extending a truth table of a stacked memory system are provided. In an example, a storage system can include a stack of first memory die configured to store data and a logic die. The logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. The logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11928363
    Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Ha Hwang, Chul-Hwan Choo, Gye Sik Oh, Young Bin Lee, Sung Won Jo
  • Patent number: 11922044
    Abstract: A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 5, 2024
    Assignee: SILICON MOTION, INC.
    Inventors: Yu-Hao Chang, Yu-Han Hsiao, Po-Sheng Chou
  • Patent number: 11922045
    Abstract: According to example embodiments of the present disclosure, a method, device and computer program product for data backup are proposed. The method comprises: obtaining a respective current value of an attribute associated with a respective backup for at least one client in a backup system and an expected time window for performing the respective backup; determining a respective duration of the respective backup based on the respective current value; and determining a respective backup time period for performing the respective backup for the at least one client based on the respective duration and the expected time window. As such, the present solution may implement automatic backup scheduling.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: March 5, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Guangjun He, Leon Yang Liu
  • Patent number: 11914509
    Abstract: Circuitry comprises memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses; in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy; the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address; in which the memory circuitry is configured to store entries as groups of entries,
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: February 27, 2024
    Assignee: Arm Limited
    Inventor: Richard Jared Cooper
  • Patent number: 11893241
    Abstract: A variable latency cache memory is disclosed. A cache subsystem includes a pipeline control circuit configured to initiate cache memory accesses for data. The cache subsystem further includes a cache memory circuit having a data array arranged into a plurality of groups, wherein different ones of the plurality of groups have different minimum access latencies due to different distances from the pipeline control circuit. A plurality of latency control circuits configured to ensure a latency is bounded to a maximum value for a given access to the data array, wherein a given latency control circuit is associated with a corresponding group of the plurality of groups. The latency for a given access may thus vary between a minimum access latency for a group closest to the pipeline control circuit to a maximum latency for an access to the group furthest from the pipeline control circuit.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: February 6, 2024
    Assignee: Apple Inc.
    Inventors: Brian P. Lilly, Sandeep Gupta, Chandan Shantharaj, Krishna C. Potnuru, Sahil Kapoor
  • Patent number: 11886308
    Abstract: A storage system has priority queues for real time-class file system messaging and backup-class file system messaging. The storage system includes servers, coupled as a storage cluster, storage devices and a network coupling the servers and the storage devices. The servers have priority queues. The servers operate the priority queues for messaging from the servers to the storage devices via the network in accordance with a real time-class file system and a backup-class file system. A first subset of the priority queues has higher priority on the network for real time-class file system messaging of at least one type. A second subset of the priority queues has lower priority on the network for backup-class file system messaging of at least one type.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 30, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Sankara Vaideeswaran, Robert Lee
  • Patent number: 11861179
    Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barak Cherches, Uri Weinrib
  • Patent number: 11861178
    Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhongguang Xu, Jian Huang, Tingjun Xie, Murong Lang, Zhenming Zhou
  • Patent number: 11853581
    Abstract: A request to restore a plurality of files to a first storage system from a backup stored at a second storage system is received. Corresponding file relocation metadata for each of the plurality of files is provided to the first storage system. The corresponding file relocation metadata for each of the plurality of files enables accessibility of contents of the plurality of files at the first storage system without storing entire contents of the plurality of files at the first storage system. A corresponding full content version for at least one of the plurality of files that is to be utilized by the first storage system is provided to enable direct access at the first storage system to contents of the at least one of the plurality of files instead of utilizing corresponding file relocation metadata for the at least one of the plurality of files to access the contents of the at least one of the plurality of files.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 26, 2023
    Assignee: Cohesity, Inc.
    Inventors: Nagapramod Mandagere, Yu-Shen Ng, Karandeep Singh Chawla
  • Patent number: 11853177
    Abstract: Methods, systems and computer program products for data protection across computing infrastructure comprising a plurality of geographically distant computing clusters. The geographically distant computing clusters form a distributed system comprising clusters that are assigned into availability zones. Disaster recovery policies are maintained in each of the availability zones. A first cluster detects a modification of a disaster recovery policy. The modification of the disaster recovery policy that occurred at the first cluster is to be communicated over a wide area network. Synchronization of the disaster recovery policy is accomplished by carrying out a peer-to-peer communication protocol over the wide area network.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Nutanix, Inc.
    Inventors: Bharat Kumar Beedu, Ganesh Sahukari, Nikhil Loya, Sharad Maheshwari
  • Patent number: 11809734
    Abstract: Embodiments manage a lifecycle of distributed data objects from at least a first data fabric node. Embodiments receive a request from a publisher to anchor a scope. Embodiments anchor the scope to an anchor in the first data fabric node to generate an anchored scope, where the anchor includes a previously published first object and a corresponding first lifecycle and anchoring the scope includes registering interest in the first lifecycle of the anchor. Embodiments publish, by the first data fabric node, scope metadata corresponding to the anchored scope. Embodiments then receive a request from the publisher to publish a second object into the anchored scope to define an anchored object, the anchored object including the first lifecycle.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 7, 2023
    Assignee: MetaFluent, LLC
    Inventor: Andrew MacGaffey
  • Patent number: 11803332
    Abstract: Systems, apparatuses, and methods related to a controller for managing sideband communications are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit can manage a first type of memory device that operates according to a first set of timing characteristics and a second type of memory device that operates according to a second set of timing characteristics. The controller can provide an additional layer of encryption or decryption for sideband communications between the host and the memory devices connected to the controller. The front end portion receives sideband communications through an interface and is stored by a cache memory within the central controller portion which also comprises an auxiliary security component to encrypt the sideband communications. The back end portion provides a route to the memory devices and the management unit applies the encryption or decryption to the sideband communication.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: October 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Massimiliano Patriarca, Massimiliano Turconi, Angelo Alberto Rovelli
  • Patent number: 11797222
    Abstract: A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: October 24, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Po-Cheng Su, Chih-Wei Wang, Wei Lin