Abstract: Systems and methods described herein allow a configurable policy for managing Power over Ethernet (PoE) to be implemented by Power Sourcing Equipments (PSEs) across a network. The policy specifies a set of rules for prioritizing power distribution over Ethernet for the computer network. When Powered Devices (PDs) are connected via Ethernet cables to the PSEs, the PDs send identification information about themselves (e.g., device type and location) to the PSEs. The PSEs assign priority levels to the PDs by electronically comparing the identification information to the set of rules. When a present level of available power is insufficient to power all the PDs via PoE, the PSEs use the priority levels to determine which PDs to power down.

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

Abstract: The technology described herein is directed towards optimizing power consumption of devices, e.g., in a datacenter. A modified (two-tier) genetic algorithm performs a carbon footprint-based optimization in a first tier to determine a candidate range of coefficients for each device type, e.g., servers, switches and storage devices/systems that likely reduce carbon footprint of each device type. In a second tier of the genetic algorithm, those ranges of coefficients are used in conjunction with actual power usage-based carbon footprint scores of individual devices to find respective sets of coefficients that minimize respective objective functions for the servers, the switches and the storage devices. The sets of coefficients can be used for power capping the devices. Device performance constraint-based intelligent selection can be used in one or both tiers to speed up convergence.

Abstract: There are provided a sensor data collection device, a sensor data collection system, and a method of collecting sensor data capable of reducing a drain of a battery due to standby power. The sensor data collection device includes a power supply, a power supply control circuit configured to control the power supply, a sensor configured to perform sensing to thereby obtain data, a memory configured to store the data obtained by the sensor, and a control circuit configured to control the power supply control circuit, the sensor, and the memory.

Abstract: An Ethernet power supply receives a DC voltage through a bus positive terminal and a bus negative terminal, and is coupled to a load device. The Ethernet power supply includes a first control module and a second control module. The first control module is used to provide a first control signal through the bus negative terminal to confirm whether the load device is a valid load. The second control module is used to connect or disconnect a coupling relationship between the bus positive terminal and the first control module according to the load device being connected or not.

Abstract: An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Abstract: Provided are methods and systems for adaptive settings for a device. An example method can comprise utilizing a first configuration setting for a feature in a device, detecting a change in a device factor, and utilizing a second configuration setting for the feature in the device in response to the detected change. Another example method can comprise detecting a change in a device factor, activating a device feature, determining whether a change threshold has been exceeded, and updating a configuration setting for a device feature if the change threshold has been exceeded.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: A processor system includes a processor and a first memory area storing a boot program code. The boot program code starts execution of the operating system when executed by the processor, performs a cryptographic operation when processor executes the boot program code. A second memory area stores one or more cryptographic keys and is only accessible to the boot program code. A third memory stores the operating system. A communication interface receives data over a communication network. The processor retrieves the boot program code from the first memory area and executes the boot program code to start execution of the operating system. The processor terminates execution of the boot program code. The processor is configured to re-execute the boot program code while the operating system is executed to cryptographically encrypt data upon the basis of the cryptographic keys stored in the second memory area.

Abstract: A system to facilitate configuration of infrastructure resources is described. The system includes a plurality of on-premises infrastructure appliances, each appliance including a plurality of infrastructure devices and an on-premises infrastructure controller to control the plurality of infrastructure devices. The system further includes a cloud services resource configuration manager, communicatively coupled to each of the on-premises infrastructure controllers, to configure each of the on-premises infrastructure appliances via a respective on-premises infrastructure controller.

Abstract: One aspect provides a power sourcing equipment controller for providing power to a powered device using power-over-Ethernet (PoE). The power sourcing equipment includes a voltage-output logic block to output a sequence of voltage signals, the voltage signals comprising at least a detection signal and a classification signal; a current-measurement logic block to measure current provided responsive to the voltage signals; a backoff-time-determination logic block to determine a backoff time in response to the current-measurement logic block detecting the provided current exceeding a predetermined threshold, the backoff time being determined based on an amount of time needed for discharging an internal capacitor associated with the powered device; and a timing logic block to cause the voltage-output logic block to delay the output of a next sequence of voltage signals based on the determined backoff time, thereby facilitating powering up of a device compliant with a different PoE standard.

Abstract: A method of adjusting core and un-core operating frequencies of two or more processors of a server includes determining core and un-core operating frequency variations versus power consumption limit variations of the two or more processors. The method also includes determining two or more first power consumption levels associated with the two or more processors. Each one of the two or more processors run at essentially a same target core operating frequency and at a same target un-core operating frequency at the respective first power consumption level of the processor. The method further includes adjusting the core and un-core operating frequencies of the two or more processors by setting a power consumption limit of each one of the two or more processors at the respective first power consumption level of the processor.

Abstract: A warning is generated when a computer simulation controller is determined to have insufficient charge to permit use through an upcoming simulation sequence. Thus, responsive to a computer simulation having a first context and a computer simulation controller having a first voltage, a human-perceptible indication of low voltage is presented, whereas if the computer simulation has a second context typically requiring less input than the first context, no indication is presented if the controller has the same first voltage.

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

Abstract: A computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, and one or more additional electronic components configured to receive electrical power from the battery. The computing device may further include a first current detector configured to detect a total battery discharge current. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit for the battery. In response to at least determining the difference, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

Abstract: SPI firmware updates can be performed at runtime. A secure SPI flash access domain can be created during pre-boot and used at runtime to deliver and write a SPI firmware update to SPI flash. The secure SPI flash access domain can ensure that only a trusted component running on a trusted CPU core can access a SPI memory layout used to deploy the SPI firmware update to the SPI flash. Once the SPI firmware update is written to the SPI flash, a reboot can be triggered so that the updated SPI firmware is loaded to perform the boot process.

Abstract: A system for securely and reliably transferring startup script files over a network may include a unified extensible firmware interface (UEFI) network stack on a client server wherein the client server requests startup script over the network upon startup of the client server using a secure transfer network protocol and receives over the network the startup script. A computing device may comprise a unified extensible firmware interface (UEFI) shell to request a download of startup script, over a network, upon startup of the client server wherein the startup script is staged in a provisioned storage device within the client server to be mounted as local file systems in the client server. The UEFI shell.

Abstract: An example computing device includes a user interface, a network interface, a non-volatile memory, a processor coupled to the user interface, the network interface, and the non-volatile memory, and a set of instructions stored in the non-volatile memory. The set of instructions, when executed by the processor, is to perform a hardware initialization of the computing device according to a setting, establish a local trust domain and a remote trust domain, use a local-access public key to issue a challenge via the user interface to grant local access to the setting, and use a remote-access public key to grant remote access via the network interface to remote access to the setting.

Abstract: Provided is a device unit, including a module, which can configure the device unit with an operating state from among different operating states during the start-up process and/or during ongoing operation of the device unit, wherein a first protected operating state of the different operating states is designed to allow the execution of at least one operating process which can be predefined and to optionally protect the operating process by means of defined cryptographic means, wherein at least one second operating state of the different operating states is designed to deactivate the first protected operating state and to allow at least one other changeable operating process and to optionally protect the operating process by means of specifiable cryptographic means.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.