Abstract: A cross-domain power control circuit is disclosed. The circuit includes a first circuit branch having a first transistor coupled to a first supply voltage node and a second circuit branch having a second transistor coupled to the first supply voltage node. A third circuit branch is coupled between a second supply voltage node and a third supply voltage node. A second supply voltage conveyed on the second supply voltage node is less than a first supply voltage conveyed on the first supply voltage node. A fourth circuit branch is coupled between the first and third supply voltage nodes. In a first mode of operation, control circuitry causes the second supply voltage to be conveyed to the third supply voltage node. In a second mode of operation, the control circuitry causes the first supply voltage to be conveyed to the third supply voltage node.

Abstract: Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.

Abstract: Reducing power consumption at an information handling system (IHS), including identifying a first data set associated with a first application, and a second data set associated with a second application; storing the first data set at a first physical storage device, and storing the second data set at a second physical storage device; reducing a power consumption of a storage device system, including: determining that the first and second applications are out-of-focus with respect to an operating system (OS) of the IHS, and in response, maintaining a low power state of the first and the second physical storage devices; detecting that the first application is in-focus with respect to the OS of the IHS, and in response, adjusting a power state of the first physical storage device from the low power state to an active power state while maintaining the low power state of the second physical storage device.

Abstract: This application relates to techniques that adjust the sleep states of a computing device based on proximity detection and predicted user activity. Proximity detection procedures can be used to determine a proximity between the computing device and a remote computing device coupled to the user. Based on these proximity detection procedures, the computing device can either correspondingly increase or decrease the amount power supplied to the various components during either a low-power sleep state or a high-power sleep state. Additionally, historical user activity data gathered on the computing device can be used to predict when the user will likely use the computing device. Based on the gathered historical user activity, deep sleep signals and light sleep signals can be issued at a time when the computing device is placed within a sleep state which can cause it to enter either a low-power sleep state or a high-power sleep state.

Abstract: An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device.

Abstract: A secure boot system, a secure boot method, and a secure boot apparatus, adapted for a boot apparatus to boot a host device, are provided. The boot apparatus includes a storage device and a processor. In the method, the processor reads a boot code and a boot key for booting the host device from the storage device, and executes a cryptographic algorithm on the boot code by using the boot key to obtain a runtime signature. Besides, the processor reads an original signature from a secure area in the storage device and uses the same to verify the runtime signature. If the runtime signature and the original signature are consistent with each other, the processor provides the boot code for the host device to execute a boot operation.

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

Abstract: A power sourcing equipment (PSE), a powered device (PD) and a line loss detection method for Power over Ethernet (PoE) are provided. The PD receives a voltage/current information transmitted by the PSE to obtain an output voltage value and an output current value thereof, and the PSE receives an input voltage value returned by the PD, such that the PSE and the PD can both calculate a line power loss therebetween based on the input voltage value of the PD, the output voltage value and the output current value of the PSE; alternatively, the PD obtains the input voltage value through a voltage detection circuit under at least one state point of a power consumption that is known, and calculates, according to the output voltage value of the PSE and a known maximum power consumption of the PD, a maximum line power loss therebetween.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

Abstract: An information handling system may include a host system comprising a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of a plurality of devices of the information handling system, and further configured to, during a powering on of the host system randomly select a subset of one or more devices of the plurality of devices for partial validation of firmware of the plurality of devices, randomly select a plurality of offsets associated with the one or more devices for partial verification of the firmware, and perform verification of the one or more devices at the plurality of offsets.

Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: Technology is described for a system that includes a power source, a first computing device, a second computing device and a host controller. The power source may provide a direct current (DC) voltage. The first computing device may perform a computing function in a computing environment. The second computing devices may be connected in series to the power source via the first computing device. The first computing device may be directly coupled to the power source and may receive the DC voltage from the power source, and the second computing device may receive a remaining amount of the DC voltage. The host controller may manage computing operations of the first computing device and the second computing device to control load impedance between first computing device and the second computing device.

Abstract: An information processing apparatus includes an ensuring circuit configured to maintain an operation of a first storage connected to a first system in a case where a detection unit detects reduction in voltage of a power supply. A control unit is configured to copy at least data necessary for activating the information processing apparatus from a second storage connected to a second system to the first storage in a case where the first storage is set not to store the data necessary for activating the information processing apparatus and a second storage is set to store the data necessary for activating the information processing apparatus.

Abstract: A control system for a terminal device includes a retrieval circuitry, a computing circuitry, a power circuitry, and a control circuitry. The retrieval circuitry is arranged to receive a plurality of electrical signals transmitted from a sensor of the terminal device. The electrical signals correspond to a first operational status thereof. The computing is arranged to determine a first variable value based on the electrical signals and a reference value. The power circuitry is arranged to retrieve a remaining power level of the terminal device, and determine a second variable value based on the remaining power level. The control circuitry is arranged to drive the terminal device to switch from the first operational status to the second operational status when the first variable value is greater than the second variable value.

Abstract: An autonomous driving system having dual secure boot is provided. The autonomous driving system includes: a control system, a host, and a baseboard management controller (BMC). The control system includes a microcontroller, a first flash memory, and a second flash memory. The first flash memory stores first embedded-controller firmware and a first application image file. The second flash memory stores second embedded-controller firmware and a second application image file. When the autonomous driving system is turned on, the microcontroller executes a dual secure boot procedure to execute the first embedded-controller firmware or the second embedded-controller firmware. In response to the microcontroller successfully executing the first embedded-controller firmware or the second embedded-controller firmware, the microcontroller authenticates the first application image file or the second application image file.

Abstract: In an aspect, the present disclosure includes a method, apparatus, and non-transitory computer readable medium for wireless communications for initiating, by a provisioning system, a provisioning procedure to configure and update a device that initiates an initial connection to a wireless network based on a unique identifier of the device; and establishing, by the provisioning system, a secure socket with the device based on the provisioning procedure.

Abstract: An electronic device according to an embodiment includes a display, and a processor including a plurality of cores, wherein the processor is configured to identify a first application satisfying a designated condition related to boosting of the processor among at least one application running on the electronic device, identify a first instruction set architecture (ISA) of the first application, and boost a frequency of a clock signal applied to at least one core among the plurality of cores included in the processor according to the first instruction set architecture.

Abstract: Systems and methods are provided for supporting use of system BIOS components (e.g., such as BIOS debug messages, debugger firmware, UEFI drivers, etc.) that are stored separately from the remainder of system BIOS firmware for an information handling system. The system BIOS components may represent only a portion of the total BIOS firmware, and may be selectively retrieved and loaded from the separate storage into system memory when needed by the system BIOS for operating purposes (e.g., such as debugging operations).

Abstract: One embodiment is directed a powered device that comprises a connector to connect a multi-conductor cable to the powered device and device circuits partitioned into a first partition and a second partition. The powered device is configured to receive power from a first cable circuit and a second cable circuit provided over the multi-conductor cable. The powered device is configured to separately power the first partition using power received from the first cable circuit and power the second partition using power received from the second cable circuit and to power isolate the first cable circuit from the second cable circuit. The powered device further comprises at least one isolation device coupled to the first partition and the second partition and configured to enable information to be communicated between the first partition and the second partition. Other embodiments are disclosed.

Abstract: Systems, apparatus, and methods that control power consumption in a processor are disclosed. One system apparatus, and method includes a processor that operates in at least a first power control mode including a first power amount and a second power control mode including a second power amount lower than the first power amount and a power control device. The power control device is configured to control power consumption in the processor, change a power control mode of the processor to the first power control mode in response to a first excess time period in which the power consumption of the processor exceeds a first reference power for a first period of time, and change the power control mode of the processor to the second power control mode in response to a second period of time in which the power consumption is less than or equal to a second reference power.